• Journal of Sensor Science and Technology
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• v.14 no.4
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• pp.237-243
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• 2005

Strain gauge type load cell is used widely as weight sensor. However, it has problems such as noise, power consumption, high cost and big size. Semiconductor type piezoresistive pressure sensor is practically used in recent for low hysteresis, good linearity, small size, light weight and strong on vibration. In this paper, we have fabricated the piezoresistive pressure sensor and packaged the miniature weight sensor. We packaged the miniature weight sensor by flip-chip bonding between die and PCB for durability, because the weight sensor is directly contacted on a physical solid distinct from air and oil pressure. We measured the characteristics of the weight sensor, which had the output of $10{\sim}80$ mV on the weight range of $0{\sim}2$ kg. In the result, we could fabricate the weight sensor with an accuracy of 3 %FSO linearity.

• Transactions on Electrical and Electronic Materials
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• v.9 no.1
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• pp.33-37
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• 2008

This paper describes the development of a new $5.0{\times}3.2mm$ SAW filter bank which is consist of 12 L, C matching components and 4 SAW bare chips on PCB substrate with CSP technology. We improved the manufacturing cost by removing the ceramic package through direct flip bonding of $LiTaO_3$ SAW bare chip on PCB board after mounting L, C passive element on PCB board. After that we realized the hermitic sealing by laminating the epoxy film. To confirm the confidentiality and durability of the above method, we have obtained the optimum flip bonding & film laminating condition, and figured out material property and structure to secure the durability & moisture proof of PCB board. The newly developed super mini $5.0{\times}3.2mm$ filter bank shows the superior features than those of existing products in confidence, electrical, mechanical characters.

• Electronics and Telecommunications Trends
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• v.9 no.1
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• pp.109-122
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• 1994

소자가 고속, 고주파화 되고 ASIC 칩의 개발이 가속화되면서 패키징과 interconnection 의 중요성이 더욱 증대되고 있다. 소자의 성능에 가장 직접적인 영향을 주는 것이 1차 패키징인데 현재 가장 많이 실행되고 있는 것이 wire 등에 의한 본딩 방법이었다. 이러한 기존의 방법은 소자의 고속화와 입출력 숫자의 증가에 따라 점차 그 한계를 보이고 있는데 이에 대한 방안으로는 플립칩 본딩 방식에 의한 패키징을 들 수 있다. 약 20여년 전에 IBM 에서 개발된 이래 많은 발전을 거듭한 이 기술은 최근 기본 기술에 대한 특허권의 소멸과 함께 많은 응용 분야에서 개발이 활발히 진행되고 있다. 따라서 본 고에서는 향후의 가장 유력한 패키징 기술로 인정되고 있는 플립칩 본딩 기술의 특징과 제조 관련 사항을 정리함과 동시에 응용 분야, 특히, OEIC(Optoelectronics Integrated Circuit) 분야에서의 이용 및 개발 현황을 분석, 소개함으로써 이 새로운 패키징 기술에 대한 인식을 제고하고자 한다.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.3
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• pp.67-73
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• 2009

Compared to the chip-bonding process utilizing solder bumps, flip chip process using Cu pillar bumps can accomplish fine-pitch interconnection without compromising stand-off height. Cu pillar bump technology is one of the most promising chip-mounting process for RF packages where large gap between a chip and a substrate is required in order to suppress the parasitic capacitance. In this study, Cu pillar bumps and Sn bumps were electroplated on a chip and a substrate, respectively, and were flip-chip bonded together. Contact resistance and chip shear force of the Cu pillar bump joints were measured with variation of the electroplated Sn-bump height. With increasing the Sn-bump height from 5 ${\mu}m$ to 30 ${\mu}m$, the contact resistance was improved from 31.7 $m{\Omega}$ to 13.8 $m{\Omega}$ and the chip shear force increased from 3.8 N to 6.8 N. On the contrary, the aspect ratio of the Cu pillar bump joint decreased from 1.3 to 0.9. Based on the variation behaviors of the contact resistance, the chip shear force, and the aspect ratio, the optimum height of the electroplated Sn bump could be thought as 20 ${\mu}m$.

• Proceedings of the Korean Society Of Semiconductor Equipment Technology
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• 2005.05a
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• pp.79-83
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• 2005

IT 기술, 반도체 산업 등의 급격한 발전에 힘입어 최근의 첨단 전자, 통신제품은 초경량 초소형화와 동시에 고기능 복합화의 발전 추세를 보이고 있다. 이런 추세에 발맞추어 전자제품, 통신제품의 핵심적인 부품인 IC chip도 소형화되고 있다. IC chip 패키징 기술의 하나인 Filp Chip Package는 Module Substrate 위에 Chip Surface를 Bumping 시킴으로서 최단의 접속길이와 저열저항, 저유전율의 특성도 가지면서 초소형에 높은 수율의 저 원가생산성을 갖는 첨단의 패키징 기술이다. 이런 패키징 기술은 수요증가와 더불어 폭발적으로 늘어나고 있으나 까다로운 공정기술에 의해 아직 여러 회사에서 장비가 출시되고 있지 못한 상태이다. 이에 본 연구에서는 최근 수요가 증가하는 LCD Driver IC용 COF 장비를 위한 Flip chip Bonding 장비 및 시스템을 설계, 제작하였다.

• Journal of the Microelectronics and Packaging Society
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• v.24 no.2
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• pp.11-15
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• 2017

As the heat dissipation problem is increased in 3D multi flip chip packages, an improvement of thermal conductivity in bonding interfaces is required. In this study, the effect of alumina filler addition was investigated in non-conductive paste(NCP). The fine alumina filler having average particles size of 400 nm for the fine pitch interconnection was used. As the alumina filler content was increased from 0 to 60 wt%, the thermal conductivity of the cured product was increased up to 0.654 W/mK at 60 wt%. It was higher value than 0.501 W/mK which was reported for the same amount of silica. It was also found out that the addition of fine sized alumina filler resulted in the smaller decrease in thermal conductivity than the larger sized particles. The viscosity of NCP with alumina addition was increased sharply at the level of 40 wt%. It was due to the increase of the interaction between the filler particles according to the finer particle size. In order to achieve the appropriate viscosity and excellent thermal conductivity with fine alumina fillers, the highly efficient dispersion process was considered to be important.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.57-64
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• 2007

New Chip-on-glass technology to attach an Si chip directly on the glass substrate of LCD panel was studied with local heating method of the Si chip by using thin film heater fabricated on the Si chip. Square-shaped Cu thin film heater with the width of $150\;{\mu}m$, thickness of $0.8\;{\mu}m$, and total length of 12.15 mm was sputter-deposited on the $5\;mm{\times}5\;mm$ Si chip. With applying current of 0.9A for 60 sec to the Cu thin film heater, COG bonding of a Si chip to a glass substrate was successfully accomplished with reflowing the Sn-3.5Ag solder bumps on the Si chip.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• Journal of the Microelectronics and Packaging Society
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• v.13 no.2 s.39
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• pp.21-26
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• 2006

We developed a bonding at low temperature using fine pitch Sn and In bumps, and studied the reliability of the fine pitch In-Sn solder joints. The $30{\mu}m$ pitch Sn and In bumps were joined together at $120^{\circ}C$. A non conductive adhesive (NCA) was applied during solder joining. Thermal cycling test ($0^{\circ}C-100^{\circ}C$, 2 cycles/h) of up to 2000 cycles was carried out to evaluate the reliability of the solder joints. The bondability was evaluated by measuring the contact resistance (Rc) of the joints through the four point probe method. As the content of filler increased, the reliability improved in the solder joints during thermal cycling test because the contact resistance increased little. The filler redistributed the stress and strains from the thermal shock over the entire joint area.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.2
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• pp.55-61
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• 2010

The device with tantalum silicide heater were bonded by Ag paste and Au SBB(Stud Bump Bonding) onto the Au coated substrate. The shear test after Au ABB and the thermal performance under current stressing were measured. The optimum condition of Au SBB was determined by fractured surface after die shear test and $350^{\circ}C$ for substrate, $250^{\circ}C$ for die during flip chip bonding with bonding load of about 300 g/bump. With applying 5W through heater on the device, the maximum temperature with Ag paste bonding was about $50^{\circ}C$. That with Au SBB on Au coated Si substrate showed $64^{\circ}C$. The difference of maximum temperatures is only $14^{\circ}C$, even though the difference of contact area between Ag paste bonding and Au SBB is by about 300 times and the simulation showed that the contact resistance might be one of the reasons.