• Journal of Welding and Joining
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• v.29 no.6
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• pp.65-70
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• 2011

The effect of flip chip bonding parameters on formation of intermetallic compounds (IMCs) between Au stud bumps and Sn-3.5Ag solder was investigated. In this study, flip chip bonding temperature was performed at $260^{\circ}C$ and $300^{\circ}C$ with various bonding times of 5, 10, and 20 sec. AuSn, $AuSn_2$ and $AuSn_4$ IMCs were formed at the interface of joints and (Au, Cu)$_6Sn_5$ IMC was observed near Cu pad side in the joint. At bonding temperature of $260^{\circ}C$, $AuSn_4$ IMC was dominant in the joint compared to other Au-Sn IMCs as bonding time increased. At bonding temperature of $300^{\circ}C$, $AuSn_2$ IMC clusters, which were surrounded by $AuSn_4$ IMC, were observed in the solder joint due to fast diffusivity of Au to molten solder with increased bonding temperature. Bond strength of Au stud bump joined with Sn-3.5Ag solder was about 23 gf/bump and fracture mode of the joint was intergranular fracture between $AuSn_2$ and $AuSn_4$ IMCs regardless bonding conditions.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2009.06a
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• pp.641-642
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• 2009

• Journal of the Korean Society of Industry Convergence
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• v.3 no.1
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• pp.69-75
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• 2000

Multichip packages are comprised of dissimilar materials which expand at different rates on heating. The differential expansion must be accommodated by the various structural elements of the package. A types of heat exposures occur operation cycles. This study presents a finite element analysis simulation of flip-chip among multichip. The effects of geometries and material properties on the reliability were estimated during the analysis of temperature and thermal stress of flip-chip. From the results, it could be obtained that the more significant parameters to the reliability of flip-chip arc chip power cycle, heat convection and height of solder bump.

• Proceedings of the Materials Research Society of Korea Conference
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• 1998.08a
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• pp.139.2-139
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• 1998

• Journal of the Microelectronics and Packaging Society
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• v.14 no.1
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• pp.19-26
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• 2007

This study was focused on the feasibility of ultrasonic bonding of Au flip chip bumps for a practical complementary metal oxide semiconductor (CMOS) image sensor with electroplated Au substrate. The ultrasonic bonding was carried out with different bonding pressures and times after the atmospheric pressure plasma cleaning, and then the die shear test was performed to optimize the ultrasonic bonding parameters. The bonding pressure and time strongly affected the bonding strength of the bumps. The Au flip chip bumps were successfully bonded with the electroplated Au substrate at room temperature, and the bonding strength reached approximate 73 MPa under the optimum conditions.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.11a
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• pp.146-150
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• 2001

Microwave model and high-frequency measurement of the ACF flip-chip interconnection was investigated using a microwave network analysis. S-parameters of on-chip and substrate were separately measured in the frequency range of 200 MHz to 20 GHz using a microwave network analyzer HP8510 and cascade probe. And the cascade transmission matrix conversion was performed. The same measurements and conversion techniques were conducted on the assembled test chip and substrate at the same frequency range. Then impedance values in ACF flip-chip interconnection were extracted from cascade transmission matrix. ACF flip chip interconnection has only below 0.1nH, and very stable up to 13 GHz. Over the 13 GHz, there was significant loss because of epoxy capacitance of ACF. However, the addition of SiO$_2$filler to the ACF lowered the dielectric constant of the ACF materials resulting in an increase of resonance frequency up to 15 GHz. High frequency behavior of metal Au stud bumps was investigated. The resonance frequency of the metal stud bump interconnects is higher than that of ACF flip-chip interconnects and is not observed at the microwave frequency band. The extracted model parameters of adhesive flip chip interconnects were analyzed with the considerations of the characteristics of material and the design guideline of ACA flip chip for high frequency applications was provided.

• Journal of the Microelectronics and Packaging Society
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• v.16 no.4
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• pp.9-15
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• 2009

Compared to the flip-chip process using solder bumps, Cu pillar bump technology can accomplish much finer pitch without compromising stand-off height. Flip-chip process with Cu pillar bumps can also be utilized in radio-frequency packages where large gap between a chip and a substrate as well as fine pitch interconnection is required. In this study, Cu pillars with and without Sn caps were electrodeposited and flip-chip-bonded together to form the Cu-Sn-Cu sandwiched joints. Contact resistances and die shear forces of the Cu-Sn-Cu sandwiched joints were evaluated with variation of the height of the Sn cap electrodeposited on the Cu pillar bump. The Cu-Sn-Cu sandwiched joints, formed with Cu pillar bumps of $25-{\mu}m$ diameter and $20-{\mu}m$ height, exhibited the gap distance of $44{\mu}m$ between the chip and the substrate and the average contact resistance of $14\;m{\Omega}$/bump without depending on the Sn cap height between 10 to $25\;{\mu}m$.

• Journal of the Korean institute of surface engineering
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• v.28 no.2
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• pp.67-76
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• 1995

The microstructure of 95wt.%Pb/5wt.%Sn and 63wt.%Sn/37wt.%Pb solders for flip chip bonding process has been characterized. Solders were deposited by thermal evaporation and reflowed in the conventional furnace or by rapid thermal annealing(RTA) process. As-deposited films show columnar structure. The microstructure of furnace cooled 63Sn/37Pb solder shows typical lamellar form, but that of RTA treated solder has the structure showing an uniform dispersion of Pb-rich phase in Sn matrix. The grain size of 95Pb/5Sn solder reflowed in the furnace is about $5\mu\textrm{m}$, but the grain size of RTA treated solder is too small to be observed. The microstructure in 63Sn/37Pb solder bump shows the segregation of Pb phase in the Sn rich matrix regardless of reflowing method. The 63Sn/37Pb solder bump formed by RTA process shows more uniform microstructure. These result are related to the heat dissipation in the solder bump.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2008.06a
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• pp.10-10
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• 2008

Flip chip technology is keeping pace with the increasing connection density of the ICs and is capable of transferring semiconductor performance to the printed circuit board. One of the most general flip chip technology is CPB technology presented by Intel. The CPTB technology has similar benefits with CPB but has simpler process and better reliability characteristics. In this paper, process sequence and structure of CPTB are presented.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.4
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• pp.9-14
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• 2007

In this study, the thermal reliability on flip chip package with non-conductive pastes (NCPs) was evaluated under accelerated conditions. As the number of thermal shock cycle and the dwell time of temperature and humidity condition increased, the electrical resistance of the flip chip package with NCPs increased. These phenomenon was occurred by the crack between Au bump and Au bump and the delamination between chip or substrate and NCPs during the thermal shock and temperature and humidity tests. And the variation of electrical resistance during temperature and humidity test was larger than that during thermal shock test. Therefore it was identified that the flip chip package with NCPs was sensitive to environment with moisture.