• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 1997.06a
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• pp.49-54
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• 1997

For the purpose of a flexible coded video transmission over a heterogeneous network, we propose a new packetization method for coded video data. The proposed method achieves small degradation of coded picture quality in case of packet discard at the network node and does not require heavy processing load for bitrate control operation. Computer simulation results show that the bitrate reduction from 384 kb/s to 192 kb/s does not cause severe degradation in picture quality.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.322-325
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• 2009

Amorphous oxide semiconductors (AOSs) are expected as new channel materials in TFTs for largearea and/or flexible FPDs, and several prototype displays have been demonstrated in these five years since the first report of AOS TFT. In this paper, we review fundamental materials science of AOSs that have been clarified to date in connection with operation characteristics of AOS TFTs.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2010.11a
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• pp.453-454
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• 2010

• Water Engineering Research
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• v.5 no.4
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• pp.157-176
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• 2004

This research presents a prototype development and implementation of Decision Support System (DSS) for integrated river basin water management for the flood control. The DSS consists of Relational Database Management System, Hydrologic Data Monitoring System, Spatial Analysis Module, Spatial and Temporal Analysis for Rainfall Event Tool, Flood Forecasting Module, Real-Time Operation of Multi Reservoir System, and Dialog Module with Graphical User Interface and Graphic Display Systems. The developed DSS provides an automated process of alternative evaluation and selection within a flexible, fully integrated, interactive, centered relational database management system in a user-friendly computer environment. The river basin decision-maker for the flood control should expect that she or he could manage the flood events more effectively by fully grasping the hydrologic situation throughout the basin.

• 한국연소학회:학술대회논문집
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• 2003.05a
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• pp.153-158
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• 2003

Catalytic Combustion used to be applied to specific conditions because of the characteristics different from flame combustion. However, many researches are focused on widening the applicant range of catalytic combustion with the competences of catalytic combustion. The development of many catalytic combustion appliances is one of the trials to overcome the restrictions of reaction and maximize the merits. In this research, past developments of appliances are depicted and new conceptual system will be introduced - sequential system. Sequential catalytic combustion system is composed of units - existing catalytic heat exchangers. This system is performed with parallel in composition and serially in operation. First, the burden of the preheating can be dramatically reduced. Second, stable operation control is expected. Lastly, Capacity expansion is flexible.

• Journal of Digital Convergence
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• v.12 no.1
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• pp.99-104
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• 2014

The purpose of this study is to explore the success factors of successful merchants. To do this, we review the successful story of merchants in Korea and Japan. We found that various success factors such as product differentiation, competitive price, flexible operation, and entrepreneurialism. As a result, it is important to find that large companies can not to do because of managerial systems. Thus, merchants have to analyze and benchmark the management strategies of competitors and development specialized managerial techniques for business operation.

• Proceedings of the IEEK Conference
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• 2000.06b
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• pp.169-172
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• 2000

This paper describes design of cryptographic processor which can execute SEED, DES, and triple DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has I unrolled loop structure with hardware sharing and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation, the precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O technique is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is designed using 2.5V 0.25 $\mu\textrm{m}$ CMOS technology and consists of about 34.8K gates. Its peak performances is about 250 Mbps under 100 Mhz ECB SEED mode and 125 Mbps under 100 Mhz triple DES mode.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.361-362
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• 2016

Presented in this paper is the design of a high voltage switch module made up of MOSFETs, pulse transformers and their gate driver circuits compactly fitted onto a single PCB module. The ease by which the switch modules can be configured (series stacking and/or parallel stacking) to meet future load variations allows for flexible operation of this design. In addition, the detailed implementation of the gate driver circuit for reliable and easier switch synchronization is also described in this paper. The stored energy in the capacitor bank of a 15kV, 4.5kJ/s peak power capacitor charger was discharged using the developed high voltage switch, and by experimental results, the operation of the proposed circuit was verified to be effectively used as a switch for pulse discharging.

• Proceedings of the KIPE Conference
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• 2001.10a
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• pp.785-789
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• 2001

Piezoelectric actuators are characterized by non-linear dynamics and high frequency oscillations of the piezocrystal. Both properties have to be taken into consideration when optimizing real time systems. Taking benefit of the almost linear behaviour between charge and strain, current source fed piezoelectric actuators are given preference for high dynamic applications. Here special emphasis is put on current sources for multi-actuator systems and the controller design for optimal system integration of the actuator. It is shown that sliding mode operation of the converter system offers good possibilities to guaranty high accuracy and dynamics of the actuators system. The presented multi-actuator system is used for positioning and vibration damping in flexible mechanical systems.

• Proceedings of the Korea Multimedia Society Conference
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• 2000.04a
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• pp.117-120
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• 2000

This paper describe VLSL design of crytographic processor which can execute triple DES and DES encryption algorithm. To satisfy flexible architecture and area-efficient structure, the processor has 1 unrolled loop structure without pipeline and can support four standard mode, such as ECB, CBC, CFB, and OFB modes. To reduce overhead of key computation , the key precomputation technique is used. Also to eliminate increase of processing time due to data input and output time, background I/O techniques is used which data input and output operation execute in parallel with encryption operation of cryptographic processor. The cryptographic processor is implemented using Altera EPF10K40RC208-4 devices and has peak performance of about 75 Mbps under 20 Mhz ECB DES mode and 25 Mbps uder 20 Mhz triple DES mode.