• Proceedings of the KIEE Conference
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• 2006.10a
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• pp.71-72
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• 2006

플라스틱 기판 위에 유도 결합 플라즈마 화학적 기상 증착장치 (Inductively Coupled Plasma Chemicai Vapor Deposition, ICP-CVD) 를 사용하여 실리콘 산화막 ($SiO_2$)을 증착하고, 엑시머레이저 어널링 (Excimer Laser Annealing, ELA) 과 $N_{2}O$ 플라즈마 전처리를 통해, 전기용량-전압(Capacitance-Voltage, C-V) 특성과 항복 전압장 (Breakdown Voltage Field) 과 같은 전기적 특성을 개선시켰다. 에너지 밀도 $250\;mJ/cm^2$ 의 엑시머 레이저 어닐링은 실리콘 산화막의 평탄 전압 (Flat Band Voltage) 을 0V에 가까이 이동시키고, 유효 산화 전하밀도 (Effective Oxide Charge Density)를 크게 감소시킨다. $N_{2}O$ 플라즈마 전처리를 통해 항복 전압장은 6MV/cm 에서 9 MV/cm 으로 향상된다. 엑시머 레이저 어닐링과 $N_{2}O$ 플라즈마 전처리를 통해 평탄 전압은 -9V 에서 -1.8V 로 향상되고, 유효 전하 밀도 (Effective Charge Density) 는 $400^{\circ}C$에서 TEOS 실리콘 산화막을 증착하는 경우의 유효 전하 밀도 수준까지 감소한다.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.241.1-241.1
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• 2013

최근 고집적화된 금속-산화막 반도체 metal oxide semiconductor (MOS) 소자는 크기가 점점 작아짐에 따라 얇은 산화막과 다양한 High-K 물질과 전극에 대하여 연구되고 있다. 이러한 소자의 열적 안정성과 균일성을 얻기 위해 다양한 열처리 방법이 사용되고 있으며, 일반적인 열처리 방법으로는 conventional thermal annealing (CTA)과 rapid thermal annealing (RTA)이 많이 이용되고 있다. 본 실험에서는 microwave radiation에 의한 열처리로 소자의 특성을 개선시킬 수 있다는 사실을 확인하였고, 상대적으로 $100^{\circ}C$ 이하의 저온에서도 공정이 이루어지기 때문에 열에 의한 소자 특성의 열화를 억제할 수 있으며, 또한 짧은 처리 시간 및 공정의 단순화로 비용을 효과적으로 절감할 수 있다. 본 실험에서는 metal-oxide-silicon (MOS) 구조의 capacitor를 제작한 다음, 기존의 CTA나 RTA 처리가 아닌 microwave radiation을 실시하여 MOS capacitor의 전기적인 특성에 미치는 microwave radiation 효과를 평가하였다. 본 실험은 p-type Si 기판에 wet oxidation으로 300 nm 성장된 SiO2 산화막 위에 titanium/aluminium (Ti/Al) 금속 전극을 E-beam evaporator로 형성하여 capacitance-voltage (C-V) 특성 및 current-voltage (I-V) 특성을 평가하였다. 그 결과, microwave 처리를 통해 flat band voltage와 hysteresis 등이 개선되는 것을 확인하였고, microwave radiation 파워와 처리 시간을 최적화하였다. 또한 일반적인 CTA 열처리 소자와 비교하여 유사한 전기적 특성을 확인하였다. 이와 같은 microwave radiation 처리는 매우 낮은 온도에서 공정이 이루어짐에도 불구하고 시료 내에서의 microwave 에너지의 흡수가 CTA나 RTA 공정에서의 열에너지 흡수보다 훨씬 효율적으로 이루어지며, 결과적으로 산화막과 실리콘 기판의 계면 특성 개선에 매우 효과적이라는 것을 나타낸다. 따라서, microwave radiation 처리는 향후 저온공정을 요구하는 nano-scale MOSFET의 제작 및 저온 공정이 필수적인 display 소자 제작의 해결책으로 기대한다.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.47 no.3
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• pp.292-301
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• 2014

The objective of this study was to design and develop a broadband ultrasonic transducer that has both wide bandwidth and high sensitivity to measure broadband echoes related to identifying fish species. A broadband ultrasonic transducer providing a nearly flat transmitting response band of 40.2-75.5 kHz with a -12 dB bandwidth of 35.3 kHz was achieved by integrating 12 tonpilz transducer elements operating at different resonance frequencies. The average transmitting voltage response, receiving sensitivity, and figure of merit values in this frequency band were 168.4 dB (re $1{\mu}Pa/V$ at 1 m), -196.8 dB (re $1V/{\mu}Pa$), and -28.4 dB, respectively. The results suggest that bandwidth and sensitivity can be widened and improved by adjusting the array pattern and the structure of tonpilz transducer elements.

• Korean Journal of Fisheries and Aquatic Sciences
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• v.47 no.3
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• pp.302-312
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• 2014

This article describes the design and performance characteristics of a broadband ultrasonic mosaic transducer. We focus on the improved bandwidth in the high frequency band of a previously designed broadband ultrasonic transducer (Lee et al., 2014). The improvement in the pulse-echo bandwidth was achieved by employing twelve $2{\times}2$ element subarrays, operating at different resonance frequencies, and utilizing the mosaic array concept. We found that the -6 dB and -12 dB bandwidths of the newly developed broadband ultrasonic mosaic transducer, were up to 155% and 170% of the previously designed model, with a quality factor of 1.71 and 1.25, respectively. The averaged TVR (transmitting voltage response), SRT (receiving sensitivity), and FOM (figure of merit) values in a nearly flat transmitting response band, from 45 to 105 kHz providing a -12 dB bandwith of 60 kHz, were 163.3 dB (re $1{\mu}Pa/V$ at 1 m), -192.8 dB (re $1V/{\mu}Pa$), and -30.9 dB, respectively.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.6
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• pp.818-823
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• 2014

A high-gain wideband low noise amplifier (LNA) using $0.25-{\mu}m$ Gallium-Nitride (GaN) MMIC technology is presented. The LNA shows 8 GHz to 15 GHz operation by a distributed amplifier architecture and high gain with an additional common source amplifier as a mid-stage. The measurement results show a flat gain of $25.1{\pm}0.8dB$ and input and output matching of -12 dB for all targeted frequencies. The measured minimum noise figure is 2.8 dB at 12.6 GHz and below 3.6 dB across all frequencies. It consumes 98 mA with a 10-V supply. By adjusting the gate voltage of the mid-stage common source amplifier, the overall gain is controlled stably from 13 dB to 24 dB with no significant variations of the input and output matching.

• Korean Journal of Materials Research
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• v.3 no.3
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• pp.310-315
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• 1993

The effects of RT A treatment on the breakdown strengths were studied for tantalum pentoxide(${Ta_2}{O_5}$) films prepared by thermal oxidation of dc-sputtered Ta(400$\AA$) on p-type (100) Si wafer. While the relative dielectric constants of the RT A -treated specimens were not remarkably affected, the breakdown strengths of the RTA-treated specimens were greatly changed by RTA temperature and time. After the RTA treatment, the breakdown strengths of the specimens RTA-treated at the temperature below the crystallization temperature were increased to 5.4MV /cm, while those of the specimens RTA -treated at the temperature above it were decreased to 0.5MV /cm. RTA time-independence of the flat-bant voltage shift refleted that the RT A post-annealing effects on the breakdown strengths were not due to the interface reaction between the ${Ta_2}{O_5}$ layer and the Si substrate but, through the RBS analysis, to densification of the ${Ta_2}{O_5}$ films.

• Journal of Electrical Engineering and Technology
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• v.1 no.3
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• pp.396-405
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• 2006

The visual analysis of buried channel (Be) devices such as buried channel MOSFETs and CCDs (Charge Coupled Devices) is investigated to give better understanding and insight for their electrical behaviours using a 3-dimensional (3-D) numerical simulation. This paper clearly demonstrates the capability of the numerical simulation of 'EVEREST' for characterising the analysis of a depletion mode MOSFET and BC CCD, which is a simulation software package of the semiconductor device. The inverse threshold and punch-through voltages obtained from the simulations showed an excellent agreement with those from the measurement involving errors of within approximately 1.8% and 6%, respectively, leading to the channel implanted doping profile of only approximately $4{\sim}5%$ error. For simulation of a buried channel CCD an advanced adaptive discretising technique was used to provide more accurate analysis for the potential barrier height between two channels and depletion depth of a deep depletion CCD, thereby reducing the CPU running time and computer storage requirements. The simulated result for the depletion depth also showed good agreement with the measurement. Thus, the results obtained from this simulation can be employed as the input data of a circuit simulator.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1364-1369
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• 2005

In this paper, we have identified the mechanism of C-V hysteresis behavior often observed in pentacene organic thin-film transistors (OTFTs). The capacitance-voltage (C-V) characteristics were measured for pentacene OTFTs fabricated on glass substrates with MoW as gate/source/drain electrode and TEOS $SiO_2$ as gate insulator. The measurements were made at room temperature and elevated temperatures. From the room temperature measurements, we found that the hysteresis behavior was caused by hole injection into the gate insulator from the pentacene semiconductor for large negative gate voltages, resulting in the negative flat-band voltage shift. However electron injection was observed only at elevated temperatures

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1284-1287
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• 2005

Peripheral pentacene region gives a significant influence on C-V characteristics of metal-oxide-pentacene capacitor structure. When the gate voltage goes toward negative, the effect of peripheral pentacene region becomes larger. Remaining gate DC bias constant and changing small signal frequency, the capacitance of peripheral pentacene changes along with frequency so that the total capacitance value also changes. The influence of peripheral pentacene region should be removed to measure accurate C-V characteristics, because it is hard to take into account the effect of the region quantitatively. After removing the influence of peripheral pentacene region, acceptor concentration, flat band voltage and depletion width of pentacene thin film are extracted from an accurate C-V curve as $1.58{\times}10^{17}cm^{-3}$, -1.54 V and 39.4 nm, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.24 no.1
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• pp.102-109
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• 1987

This study is carrier out to investigate the carrier injection and the characteristics of trapping for the CVD deposited Al2O3 film on Si substrates. Samples used are metal -Al2O3-Si Structure in which metal field plates are used with Aluminium or God. Canier injection and trapping, which result in flat band voltalge shift, occur at fields as low as 1~2 MV/cm. An approximate method is proposed for computing the location of the centroid of the trapped electrons in this paper. Results show that carriers are trapped near the injecting interface at fields less than about 5MV/cm. Because of continued charging, a steady state can not be reached. Therefore the unique I-V curve is obtained when the traps are initially empty. By utilization of applied voltage on each point of the fresh device sample, it is measured the I-V surves for two polarities of applied voltage. The current densities observed in the Al2O3 films are much larger than those obtained in SiO2.