• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1580-1582
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• 2007

The composites were fabricated with titania used commercially and calcite as a filler in BZB glass matrix and their thermal, optical and electrical properties were investigated. From our results, calcite may be the profitable and highly efficient reflectance material as a filler for flat panel display devices.

• The Magazine of the IEIE
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• v.22 no.3
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• pp.92-105
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• 1995

각 분야에서 고화질 고해상도의 Flat Panel Display(FPD)에 대한 요구가 급증하고 있으며, FPD 소자들도 다양하다. FPD를 위한 구동방식은 근본적으로 matrix addroessing 방식을 사용하지만 FPD 소자의 동작 원리, 특성, 구동상의 문제점 등에 따라서 구동방식도 매우 다양하다. 다양한 FPD 소자들이 구동 방식과 구동회로를 다 살펴볼 수 없으므로 본고에서는 FPD소자인 PDP, EL, LED, EC, LCD, DMD, AMA, GLV, FED 등의 동작 원리를 설명하고, 이 소자들 중에서 AMLCD와 dc-PDP 소자의 구동방식과 구동회로에 대하여 논의한다. AMLCD의 구동방식으로는 펄스 구동 방식과 용량 구동 방식을 살펴보고, AMLCD의 문제점들을 극복할 수 있는 방법들을 설명한다. dc-PDP의 구동 방법인 pulse-memory 구동방식과 새로운 pulse-memory 구동 방식을 살펴보았다.

• 한국정보디스플레이학회:학술대회논문집
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• 2005.07b
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• pp.1067-1070
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• 2005

A large size flat panel LCD-TV must fulfill different requirements than a desktop LCD-monitor: The contrast must be much larger, the viewing angle should be as wide as possible and the switching times must be shorter to allow moving pictures to be displayed naturally. The "Vertically Aligned" technology is most promising to realize such a product. LC-material development for this technology began at Merck about 10 years ago. New materials based on the 1,1,6,7-tetrafluoroindane skeleton were recently synthesized via ortho-metallation and intramolecular Heck cyclization followed by an oxidative fluorination procedure. The materials offer improved properties over liquid crystals currently employed in flat panel LCD-TVs.

• Proceedings of the Korean Society of Medical Physics Conference
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• 2006.08a
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• pp.47-47
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• 2006

• Proceedings of the Korean Society of Medical Physics Conference
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• 2006.08a
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• pp.46-46
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• 2006

• Journal of the Korean Society for Precision Engineering
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• v.16 no.8
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• pp.23-27
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• 1999

The measurement of thr high-temperature strains is one of the challenging subjects in mechanical engineering. For the precise measurement, proper high-temperature strain gauge, cement and skilled technique are needed. In this paper, a high-temperature strain measurement is performed for the perfectly flat CRT. As this CRT is structurally very weak, cracking of the panel frequently occurs during the heat cycle in the furnace. From the measured strain variations of the panel with tension shadow mask, the crack behavior can be explained.

• Journal of the Society of Naval Architects of Korea
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• v.32 no.2
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• pp.32-42
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• 1995

When the thickness becomes so small as in the case of the trailing edge of the propeller blade or when the curvature of the surface varies rapidly as in ship stem, the existing panel method employing a flat-surface panel, obtained by collapsing the original non-planar surface into its mean location, suffers the leakage problem and also gives inaccurate induction upon the field point very close to the panel. The hyperboloidal panel deals with the induction from the dipole distributed on the non-planar surface without approximation, overcoming the defects of the flat-surface panel. This paper introduces two distinct derivations of the formulae to compute the integral for the potential induced by a dipole of uniform density distributed on a non-planar hyperboloidal surface element. One method is based on the Gauss-Bonnet theorem and the other is based on the transformation of the surface integral into a line integral.

• The monthly packaging world
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• s.145
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• pp.87-91
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• 2005

• Information Display
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• v.14 no.2
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• pp.20-31
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• 2013

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.2
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• pp.1-6
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• 2002

In this paper, an Analog Flat Panel interface(AFPI) which supports for UXGa(Ultar extended Graphics Array)-Compatible TFT LCD Driver is designed. The Proposed AFPI is composed of 8-b ADC, Automatic Gain Control(AGC), Low-Jitter PLL. In order to obtain a high speed and low power consumption, an efficient architecture of 8-bit ADC is proposed, whose FR(Folding Rate) is 8, NFB(Number of Folding Block) is 2, and IR (Interpolating Rate) is 16. We can get high SNDR by adopting distributed track and hold circuits. Also a programmable AGC which is possible to control gain and clamp, and a low-jitter PLL are proposed. The chip has been fabricated with 0.25${\mu}{\textrm}{m}$ 1-poly S-metal n-well CMOS technology. The effective chip area is 3.6mm $\times$ 3.2mm and it dissipates about 602㎽ at 2.5V power supply. The INL and DNL are within $\pm$ 1LSB. The measured SNDR is about 43㏈, when the input frequency is 10MHz at 200MHz clock frequency.