• KIPS Transactions on Computer and Communication Systems
• /
• v.5 no.1
• /
• pp.1-6
• /
• 2016

This paper focuses on algorithm innovation of NAND Flash Memory for enhancing cell lifetime. During flash memory read/write/erase, the voltage of a specific cell should be a valid voltage level. If not, we cannot read the data correctly. This type of interference/disturbance tends to be serious when program and erase operation will go on. This is because FN tunneling results in tunnel oxide damage due to increased trap site on repetitive high biased state. In order to resolve this problem, we make the cell degradation by reducing the amount of stress in terms of erase cell, resulting in minimizing the cell disturbance on erase verify.

• The Journal of the Korea institute of electronic communication sciences
• /
• v.10 no.2
• /
• pp.275-282
• /
• 2015

Since a NAND-flash memory is able to keep data during electricity-off and has small cost to store data per bytes, it is widely used on hand-held devices. It is necessary to use an index in order to process mass data effectively on the flash memory. However, since the flash memory requires high cost for a write operation and does not support an overwrite operation, it is possible to reduce the performance of the index when the disk based index is exploited. In this paper, we implement the fixed grid file index and evaluate the performance of the index on various conditions. To do this, we measure the average processing time by the ratio of query operations and update operations. We also the compare the processing times of the flash memory with those of the magnetic disk.

• IEMEK Journal of Embedded Systems and Applications
• /
• v.18 no.1
• /
• pp.31-40
• /
• 2023

Recent advances in flash technologies, such as 3D processing and multileveling schemes, have successfully increased the flash capacity. Unfortunately, these technology advances significantly degrade flash's reliability due to a smaller cell geometry and a finer-grained cell state control. In this paper, we propose an asymmetric BER-aware reliability optimization technique (aBARO), new flash optimization that improves the flash reliability. To this end, we first reveal that bit errors of 3D NAND flash memory are highly skewed among flash cell states. The proposed aBARO exploits the unique per-state error model in flash cell states by selecting the most error-prone flash states and by forming narrow threshold voltage distributions (for the selected states only). Furthermore, aBARO is applied only when the program time (tPROG) gets shorter when a flash cell becomes aging, thereby keeping the program latency of storage systems unchanged. Our experimental results with real 3D MLC and TLC flash devices show that aBARO can effectively improve flash reliability by mitigating a significant number of bit errors. In addition, aBARO can also reduce the read latency by 40%, on average, by suppressing the read retries.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.49 no.4
• /
• pp.26-33
• /
• 2012

As the flash memory has increased the market share of data storage in imbedded system and occupied the most of area in a system, It has a profound impact on system reliability. Flash memory is divided NOR/NAND-type according to the cell array structure, and is classified as SLC(Single Level Cell)/MLC(Multi Level Cell) according to reference voltage. Although NAND-type flash memory is slower than NOR-type, but it has large capacity and low cost. Also, By the effect of demanding mobile market, MLC NAND-type is widely adopted for the purpose of the multimedia data storage. Accordingly, Importance of fault detection algorithm is increasing to ensure MLC NAND-type flash memory reliability. There are many researches about the testing algorithm used from traditional RAM to SLC flash memory and it detected a lot of errors. But the case of MLC flash memory, testing for fault detection, there was not much attempt. So, In this paper, Extend SLC NAND-type flash memory fault detection algorithm for testing MLC NAND-type flash memory and try to reduce these differences.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.13 no.2
• /
• pp.315-320
• /
• 2009

Since flash memory can not be overwritten on updating data, new data are updated in new area and old data should be invalidated and erased for garbage collection. With develop of flash memory technology, capacity of flash memory is rapidly increasing. It increases rapidly execution time of CPU to search an entire flash memory of large capacity when choosing the block to erase in garbage collection. To solve the problem that is increasing execution time of CPU, flash memory is partitioned into several groups, the block to erase in garbage collection is searched within the corresponding group. In workload of access locality, we enhanced wear-leveling within group by allocating hot data to hot group and cold data to cold group respectively and enhanced wear-leveling among groups by exchanging periodically hot group and cold group.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2014.02a
• /
• pp.236.2-236.2
• /
• 2014

세계 반도체 시장은 컴퓨터 기능이 더해진 모바일 기기의 수요가 증가함에 따라 메모리반도체의 시장규모가 최근 빠른 속도로 증가했다. 특히 모바일 기기에서 저장장치 역할을 하는 비휘발성 반도체인 NAND Flash Memory는 스마트폰 및 태블릿PC 등 휴대용 기기의 수요 증가, SSD (Solid State Drive)를 탑재한 PC의 수요 확대, 서버용 SSD시장의 활성화 등으로 연평균 18.9%의 성장을 보이고 있다. 이러한 경제적인 배경 속에서 NAND Flash 미세공정 기술의 마지막 단계로 여겨지는 1Xnm 공정이 개발되었다. 그러나 1Xnm Flash Memory의 생산은 새로운 제조설비 구축과 차세대 공정 기술의 적용으로 제조비용이 상승하는 단점이 있다. 이에 따라 제조공정기술을 미세화하지 않고 기존의 수평적 셀구조에서 수직적 셀구조로 설계 구조를 다양화하는 기술이 대두되고 있는데 이 중 Flash Memory의 대용량화와 수명 향상을 동시에 추구할 수 있는 3D NAND 기술이 주목을 받게 되면서 공정기술의 변화도 함께 대두되고 있다. 3D NAND 기술은 기존라인에서 전환하는데 드는 비용이 크지 않으며, 노광장비의 중요도가 축소되는 반면, 증착(Chemical Vapor Deposition) 및 식각공정(Etching)의 기술적 난이도와 스텝수가 증가한다. 이 중 V-NAND 3D 기술에서 사용하는 박막증착 공정의 경우 산화막과 질화막을 번갈아 증착하여 30layer 이상을 하나의 챔버 내에서 연속으로 증착한다. 다층막 증착 공정이 비정상적으로 진행되었을 경우, V-NAND Flash Memory를 제조하기 위한 후속공정에 영향을 미쳐 웨이퍼를 폐기해야 하는 손실을 초래할 수 있다. 본 연구에서는 V-NAND 다층막 증착공정 중에 다층막의 두께를 가상 계측하는 알고리즘을 개발하고자 하였다. 증착공정이 진행될수록 박막의 두께는 증가하여 커패시터 관점에서 변화가 생겨 RF 신호의 진폭과 위상의 변화가 생긴다는 점을 착안하여 증착 공정 중 PECVD 장비 RF matcher와 heater에서 RF 신호의 진폭과 위상을 실시간으로 측정하여 데이터를 수집하고, 박막의 두께와의 상관성을 분석하였다. 이 연구 결과를 토대로 V-NAND Flash memory 제조 품질향상 및 웨이퍼 손실 최소화를 실현하여 제조 시스템을 효율적으로 운영할 수 있는 효과를 기대할 수 있다.

• Journal of the Institute of Electronics Engineers of Korea CI
• /
• v.47 no.5
• /
• pp.41-49
• /
• 2010

Being popularized the use of portable entertainment/information devices, the demand on flash memory has been also increased radically. In general, flash memory reveals various error patterns by the devices it is mounted, and thus the memory makers are trying to minimize error ratio in the final process through not only the electric test but also the data integrity test under the same condition as real application devices. This process is called an application-level memory test. Though currently various flash memory testing devices have been used in the production lines, most of the works related to memory test depend on the sensual abilities of human testers. In case of testing the flash memory for MP3 devices, the human testers are checking if the memory has some errors by hearing the audio played on the memory testing device. The memory testing process like this has become a bottleneck in the flash memory production line. In this paper, we propose an audio comparison technique to support the efficient flash memory test for MP3 devices. The technique proposed in this paper compares the variance change rate between the source binary file and the decoded analog signal and checks automatically if the memory errors are occurred or not.

• Journal of KIISE:Computing Practices and Letters
• /
• v.16 no.1
• /
• pp.17-22
• /
• 2010

As deployments of Flash memory are spreading out rapidly from tiny USB storages to large DB servers, interoperability become an indispensable requirement for Flash memory software architecture. For the purpose, many systems make use of the conventional FAT file system and FTL (Flash Translation Layer) software as a de facto standard. However, the tactless combination of the FAT file system and FTL does not satisfy diverse other requirements of a variety of systems. In this paper, we propose a novel reconfigurable integrated Flash memory software architecture, named INFLAWARE (INtegrated FLAsh softWARE) that supports not only interoperability but also reconfigurability and performance enhancement. Real implementation based experimental results have shown that INFLAWARE can achieve improvements of memory footprint up to 27% with an average of 19%, compared with the conventional FAT and FTL combination. Also, by using map_destroy technique, it can reduce response times of various applications up to 21% with an average of 10%.

• The KIPS Transactions:PartD
• /
• v.18D no.3
• /
• pp.157-168
• /
• 2011

Recently flash memory has been being utilized as a main storage device in mobile devices, and flashSSDs are getting popularity as a major storage device in laptop and desktop computers, and even in enterprise-level server machines. Unlike HDDs, on flash memory, the overwrite operation is not able to be performed unless it is preceded by the erase operation to the same block. To address this, FTL(Flash memory Translation Layer) is employed on flash memory. Even though the modified data block is overwritten to the same logical address, FTL writes the updated data block to the different physical address from the previous one, mapping the logical address to the new physical address. This enables flash memory to avoid the high block-erase cost. A flashSSD has an array of NAND flash memory packages so it can access one or more flash memory packages in parallel at once. To take advantage of the internal parallelism of flashSSDs, it is beneficial for DBMSs to request I/O operations on sequential logical addresses. However, the B-tree structure, which is a representative index scheme of current relational DBMSs, produces excessive I/O operations in random order when its node structures are updated. Therefore, the original b-tree is not favorable to SSD. In this paper, we propose AS(Always Sequential) B-tree that writes the updated node contiguously to the previously written node in the logical address for every update operation. In the experiments, AS B-tree enhanced 21% of B-tree's insertion performance.

• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.777-778
• /
• 2006

In this thesis, we design and implement a Flash Cache Core Module (FCCM) which operates on the YAFFS NAND flash memory. The FCCM applies memory replacement policy and prefetching policy based on the page reference pattern of applications. Also, implement the Clean-First memory replacement technique considering the characteristics of flash memory. In this method the decision is made according to page hit to apply prefetched waiting area. The FCCM decrease I/O hit frequency up to 37%, Compared with the linux cache and prefetching policy. Also, it operated using less memory for prefetching(maximum 24% and average 16%) compared with the linux kernel.