• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.2
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• pp.121-129
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• 2011

It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 $mm^2$ (16.79 mm ${\times}$ 10.68 mm) in 3 metal 26 nm CMOS.

• ETRI Journal
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• v.36 no.5
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• pp.876-879
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• 2014

In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory - namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit-line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid-state drive.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2004.05a
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• pp.91-94
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• 2004

Preform design techniques have been investigated in efforts to reduce die wear and forming load and to improve material flow, filing ratio, etc. In hot forging processes, a thin deformed part of a workpiece, known as a flash, is formed in the narrow gap between the upper and lower tools. Although designers make tools that generate a flash intentionally in order to improve flow properties, excessive flash increases die wear and forming load. Therefore, it is necessary to make a preform shape that can reduce the excessive flash without changing flow properties. In this paper, a new preform design technique is proposed to reduce the excessive flash in a metal forging process. After a finite element simulation of the process is carried out with an initial billet, the flow of material in the flash region is traced from the final shape to the initial billet. The region belonging to the flash is then easily found in the initial billet. The finite element simulation is then carried out again with the modified billet from which the selected region has been removed. In several iterations of this technique, the optimal preform shape that minimizes the amount of flash without changing the forgeability can be obtained.

• Transactions of Materials Processing
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• v.13 no.6 s.70
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• pp.503-508
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• 2004

Preform design techniques have been investigated to reduce die wear and forming load and to improve material flow, filling ratio, etc. In hot forging processes, a thin deformed part of a workpiece, known as a flash, is formed in the narrow gap between the upper and lower tools. Although designers make tools that generate a flash intentionally in order to improve flow properties, excessive flash increases die wear and forming load. Therefore, it is necessary to make a preform shape that can reduce the excessive flash without changing flow properties. In this paper, a new preform design technique is proposed to reduce the excessive flash in a metal forging process. After a finite element simulation of the process is carried out with an initial billet, the flow of material in the flash region is traced from the final shape to the initial billet. The region belonging to the flash is then easily found in the initial billet. The finite element simulation is then carried out again with the modified billet from which the selected region has been removed. In several iterations of this technique, the optimal preform shape that minimizes the amount of flash without changing the forgeability can be obtained.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.537-542
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• 2014

The three-dimensional (3-D) NAND flash structure with fully charge storage using edge fringing field effect is presented, and its programming characteristic is evaluated. We successfully confirmed that this structure using fringing field effect provides good program characteristics showing sufficient threshold voltage ($V_T$) margin by technology computer-aided design (TCAD) simulation. From the simulation results, we expect that program speed characteristics of proposed structure have competitive compared to other 3D NAND flash structure. Moreover, it is estimated that this structural feature using edge fringing field effect gives better design scalability compared to the conventional 3D NAND flash structures by scaling of the hole size for the vertical channel. As a result, the proposed structure is one of the candidates of Terabit 3D vertical NAND flash cell with lower bit cost and design scalability.

• Journal of Korea Game Society
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• v.5 no.3
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• pp.11-16
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• 2005

As an improvement of the CPU performance of mobile terminals and an increase of user requirements for multimedia services, various multimedia services and applications have been developed and served over mobile platforms. In this paper, we describe the design and implementation of the Mobile Flash which is one of the famous services in mobile platforms with the limitation of hardware resources. The Mobile flash is an optimized solution for mobile terminals of the Flash, which has been used in the Internet browsers not less than 95% in the world for playing various types of contents such as animations, games, contents for education, e-commerce.

• IEMEK Journal of Embedded Systems and Applications
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• v.6 no.5
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• pp.263-272
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• 2011

The complexity of flash memory based storage systems is high due to diverse host interfaces and other design choices such as mapping granularity, flash memory controller execution models and so on. Thus, it is possible that the actual performance after implementation is not consistent with the target performance. This paper demonstrates that the performance prediction of flash memory based storage systems is possible through performance modeling that takes into account various design parameters. In the performance modeling, the FTL, which is the core element of flash memory based storage systems, is modeled as a set of (copy-on-write) logs and their interactions. Also, the flash memory controller is modeled based on the classification proposed in the design of the Ozone flash controller. In this study, the performance model has been implemented using Simulink and experimental results are presented and analyzed.

• Proceedings of the Korea Society of Design Studies Conference
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• 2003.11a
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• pp.66-67
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• 2003

• Journal of IKEEE
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• v.25 no.4
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• pp.778-781
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• 2021

In this paper, we propose the 16-layer 3D NAND Flash memory compact modeling using SPICE. In the same structure and simulation conditions, the channel potential about Down Coupling Phenomenon(DCP) and Natural Local Self Boosting (NLSB) were simulated and analyzed with Technology Computer Aided Design(TCAD) tool Atlas(Silvaco^TM) and SPICE, respectively. As a result, it was confirmed that the channel potential of TCAD and SPICE for the two phenomena were almost same. The SPICE can be checked the device structure intuitively by using netlist. Also, its simulation time is shorter than TCAD. Therefore, using SPICE can be expected to efficient research on 3D NAND Flash memory.

• IEMEK Journal of Embedded Systems and Applications
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• v.10 no.3
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• pp.151-156
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• 2015

Recently, an embedded flash memory has been widely used for the Internet of Things(IoT). Due to its nonvolatility, economical feasibility, stability, low power usage, and fast speed. With respect to power consumption, the embedded memory system must consider the most significant design factor. The objective of this research is to design high performance and low power NAND flash memory architecture including a dual buffer as a replacement for NOR flash. Simulation shows that the proposed NAND flash system can achieve better performance than a conventional NOR flash memory. Furthermore, the average memory access time of the proposed system is better that of other buffer systems with three times more space. The use of a small buffer results in a significant reduction in power consumption.