• JSTS:Journal of Semiconductor Technology and Science
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• 제11권2호
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• pp.121-129
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• 2011

It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20nm technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 $mm^2$ (16.79 mm ${\times}$ 10.68 mm) in 3 metal 26 nm CMOS.

• ETRI Journal
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• 제36권5호
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• pp.876-879
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• 2014

In current NAND flash design, one of the most challenging issues is reducing peak current consumption (peak ICC), as it leads to peak power drop, which can cause malfunctions in NAND flash memory. This paper presents an efficient approach for reducing the peak ICC of the cache program in NAND flash memory - namely, a program Cache Busy Time (tPCBSY) control method. The proposed tPCBSY control method is based on the interesting observation that the array program current (ICC2) is mainly decided by the bit-line bias condition. In the proposed approach, when peak ICC2 becomes larger than a threshold value, which is determined by a cache loop number, cache data cannot be loaded to the cache buffer (CB). On the other hand, when peak ICC2 is smaller than the threshold level, cache data can be loaded to the CB. As a result, the peak ICC of the cache program is reduced by 32% at the least significant bit page and by 15% at the most significant bit page. In addition, the program throughput reaches 20 MB/s in multiplane cache program operation, without restrictions caused by a drop in peak power due to cache program operations in a solid-state drive.

• 한국소성가공학회:학술대회논문집
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• 한국소성가공학회 2004년도 춘계학술대회 논문집
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• pp.91-94
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• 2004

Preform design techniques have been investigated in efforts to reduce die wear and forming load and to improve material flow, filing ratio, etc. In hot forging processes, a thin deformed part of a workpiece, known as a flash, is formed in the narrow gap between the upper and lower tools. Although designers make tools that generate a flash intentionally in order to improve flow properties, excessive flash increases die wear and forming load. Therefore, it is necessary to make a preform shape that can reduce the excessive flash without changing flow properties. In this paper, a new preform design technique is proposed to reduce the excessive flash in a metal forging process. After a finite element simulation of the process is carried out with an initial billet, the flow of material in the flash region is traced from the final shape to the initial billet. The region belonging to the flash is then easily found in the initial billet. The finite element simulation is then carried out again with the modified billet from which the selected region has been removed. In several iterations of this technique, the optimal preform shape that minimizes the amount of flash without changing the forgeability can be obtained.

• 소성∙가공
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• 제13권6호
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• pp.503-508
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• 2004

Preform design techniques have been investigated to reduce die wear and forming load and to improve material flow, filling ratio, etc. In hot forging processes, a thin deformed part of a workpiece, known as a flash, is formed in the narrow gap between the upper and lower tools. Although designers make tools that generate a flash intentionally in order to improve flow properties, excessive flash increases die wear and forming load. Therefore, it is necessary to make a preform shape that can reduce the excessive flash without changing flow properties. In this paper, a new preform design technique is proposed to reduce the excessive flash in a metal forging process. After a finite element simulation of the process is carried out with an initial billet, the flow of material in the flash region is traced from the final shape to the initial billet. The region belonging to the flash is then easily found in the initial billet. The finite element simulation is then carried out again with the modified billet from which the selected region has been removed. In several iterations of this technique, the optimal preform shape that minimizes the amount of flash without changing the forgeability can be obtained.

• JSTS:Journal of Semiconductor Technology and Science
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• 제14권5호
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• pp.537-542
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• 2014

The three-dimensional (3-D) NAND flash structure with fully charge storage using edge fringing field effect is presented, and its programming characteristic is evaluated. We successfully confirmed that this structure using fringing field effect provides good program characteristics showing sufficient threshold voltage ($V_T$) margin by technology computer-aided design (TCAD) simulation. From the simulation results, we expect that program speed characteristics of proposed structure have competitive compared to other 3D NAND flash structure. Moreover, it is estimated that this structural feature using edge fringing field effect gives better design scalability compared to the conventional 3D NAND flash structures by scaling of the hole size for the vertical channel. As a result, the proposed structure is one of the candidates of Terabit 3D vertical NAND flash cell with lower bit cost and design scalability.

• 한국게임학회 논문지
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• 제5권3호
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• pp.11-16
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• 2005

최근 모바일 휴대 단말기의 성능 향상과 사용자의 멀티미디어 서비스에 대한 요구 수준이 높아짐에 따라 모바일 휴대 단말에서 다양한 멀티미디어 응용 프로그램들이 개발/서비스되고 있다. 본 논문은 현재 모바일 환경에서 대표적인 멀티미디어 서비스의 하나인 Mobile Flash를 하드웨어 리소스 제약이 많은 모바일 환경에서 설계 및 구현한 것에 관하여 기술한다. Mobile Flash는 유선 데스크탑 환경에서 이미 전세계의 95% 이상 보급/설치되어 애니메이션, 게임, 교육용 컨텐츠, 광고 등 다양한 컨텐츠를 재생을 지원하는 Flash Player를 모바일 환경에 맞도록 최적화한 것이다.

• 대한임베디드공학회논문지
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• 제6권5호
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• pp.263-272
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• 2011

The complexity of flash memory based storage systems is high due to diverse host interfaces and other design choices such as mapping granularity, flash memory controller execution models and so on. Thus, it is possible that the actual performance after implementation is not consistent with the target performance. This paper demonstrates that the performance prediction of flash memory based storage systems is possible through performance modeling that takes into account various design parameters. In the performance modeling, the FTL, which is the core element of flash memory based storage systems, is modeled as a set of (copy-on-write) logs and their interactions. Also, the flash memory controller is modeled based on the classification proposed in the design of the Ozone flash controller. In this study, the performance model has been implemented using Simulink and experimental results are presented and analyzed.

• 한국디자인학회:학술대회논문집
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• 한국디자인학회 2003년도 가을학술발표대회
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• pp.66-67
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• 2003

• 전기전자학회논문지
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• 제25권4호
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• pp.778-781
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• 2021

본 논문에서는 SPICE를 사용한 16단 3D NAND Flash memory compact modeling을 제안한다. 동일한 structure와 simulation 조건에서 Down Coupling Phenomenon(DCP)과 Natural Local Self Boosting(NLSB)에 대한 channel potential을 Technology Computer Aided Design(TCAD) tool Atlas(Silvaco^TM)와 SPICE로 simulation하고 분석했다. 그 결과 두 현상에 대한 TCAD와 SPICE의 channel potential이 매우 유사한 것을 확인할 수 있었다. SPICE는 netlist를 통해 소자 structure를 직관적으로 확인할 수 있다. 또한, simulation 시간이 TCAD에 비해 짧게 소요된다. 그러므로 SPICE를 이용하여 3D NAND Flash memory의 효율적인 연구를 기대할 수 있다.

• 대한임베디드공학회논문지
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• 제10권3호
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• pp.151-156
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• 2015

Recently, an embedded flash memory has been widely used for the Internet of Things(IoT). Due to its nonvolatility, economical feasibility, stability, low power usage, and fast speed. With respect to power consumption, the embedded memory system must consider the most significant design factor. The objective of this research is to design high performance and low power NAND flash memory architecture including a dual buffer as a replacement for NOR flash. Simulation shows that the proposed NAND flash system can achieve better performance than a conventional NOR flash memory. Furthermore, the average memory access time of the proposed system is better that of other buffer systems with three times more space. The use of a small buffer results in a significant reduction in power consumption.