• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.205-210
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• 2007

This paper presents a CMOS TIQ flash A/D converter which operates very fast compared to other types of A/D converters due to its parallel architecture. The output resolution of designed A/D converter is 6-bit. In order to reduce the power consumption and chip area of conventional flash A/D converter, TIQ based flash A/D converter is proposed, which uses the advantage of the structure of CMOS transistors. The length and width of transistors of TIQ were determined with HSPICE simulation. To speed up the ultra-high speed flash A/D converter, the Fat Tree Encoder technique is used. The TIQ A/D converter was designed with full custom method. The chip's maximum power consumption was 38.45mW at 1.8V, and the operating speed of simulation was 2.7 GSPS.

• Proceedings of the KIEE Conference
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• 2004.11c
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• pp.626-628
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• 2004

This paper describes an 8-bit CMOS folding A/D converter for set-top box. Modular low-power, high-speed CMOS A/D converter for embedded systems aims at design techniques for low-power, high-speed A/D converter processed by the standard CMOS technology. The time-interleaved A/D converter or flash A/D converter are not suitable for the low-power applications. The two-step or multi-step flash A/D converters need a high-speed SHA, which represents a tough task in high-speed analog circuit design. On the other hand, the folding A/D converter is suitable for the low-power, high-speed applications(Embedded system). The simulation results illustrate a conversion rate of 40MSamples/s and a Power dissipation of 80mW(only analog block) at 2.5V supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.4
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• pp.613-618
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• 2015

This paper proposed a low power CMOS Flash-SAR A/D converter which consists of a Flash A/D converter for 2 most significant bits and a SAR A/D converter with capacitor D/A converter for 8 least significant bits. Employment of a Flash A/D converter allows the proposed circuit to enhance the conversion speed. The SAR A/D converter with capacitor D/A converter provides a low power dissipation. The proposed A/D converter consumes $136{\mu}W$ with a power supply of 1V under a $0.18{\mu}m$ CMOS process and achieves 9.16 effective number of bits for sampling frequency up to 2MHz. Therefore it results in 120fJ/step of Figure of Merit (FoM).

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.599-603
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• 1988

In this paper, a flash type A/D converter using Variable Threshold Logic circuit is designed and is layonted by double metal CMOS 2 um design rule. Comparator and register string which is the basic elements of a general flash type A/D converter are substituted by simple comparator circuit which is slightly modified from cmos inverter.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.16-23
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• 2010

This paper presents 6bit 250MS/s flash A/D converter which can be applied to wireless communication system. To solve the problem of large power consumption in flash A/D converter, control algorithm by input signal level is used in comparator stage. Also, input voltage range detector circuit is used in reference resistor array to minimize the dynamic power consumption in the comparator. Compared with the conventional A/D converter, the proposed A/D converter shows 4.3% increase of power consumption in analog and a seventh power consumption in digital, which leads to a half of power consumption in total. The A/D converter is implemented in a $0.18{\mu}m$ CMOS 1-poly 6-metal technology. The measured results show 106mW power dissipation with 1.8V supply voltage. It shows 4.1bit ENOB at sampling frequency 250MHz and 30.27MHz input frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.11C
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• pp.963-969
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• 2008

This paper presents 6bit 100MHz Interpolation Flash Analog-to-Digital Converter, which can be applied to the Receiver of Wireless Tele-communication System. The 6bit 100MHz Flash Analog-to-Digital Converter simplifies and integrates S-R latch which multiplies as the resolution increases. Whereas the conventional NAND based S-R latch needed eight MOS transistors, this Converter was designed with only six, which makes the Dynamic Power Dissipation of the A/D Converter reduced up to 12.5%. The designed A/D Converter went through $0.18{\mu}m$ CMOS n-well 1-poly 6-metal process to be a final product, and the final product has shown 282mW of power dissipation with 1.8V of Supply Voltage, 100MHz of conversion rate. And 35.027dBc, 31.253dB SFDR and 4.8bits, 4.2bits ENOB with 12.5MHz, 50MHz of each input frequency.

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.305-308
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• 2002

An 1.8V 6bit IGSPS ADC for high speed data acquisition is discussed in this paper. This ADC is based on a flash ADC architecture because the flash ADC is the only practical architecture at conversion rates of IGSPS and beyond. A straightforward 6bit full flash A/D converter consists of two resistive ladders with 63 laps, 63 comparators and digital blocks. One important source of errors in flash A/D converter is caused by the capacitive feedthrough of the high frequency input signal to the resistive reference-lauder. Consequently. the voltage at each tap of the ladder network can change its nominal DC value. This means large transistors have a large parasitic capacitance. Therefore, a dual resistive ladder with capacitor is employed to fix the DC value. Each resistive ladder generates 32 clean reference voltages which alternates with each other. And a two-stage amplifier is also used to reduce the effect of the capacitive feedthrough by minimizing the size of MOS connected to reference voltage. The proposed ADC is based on 0.18${\mu}{\textrm}{m}$ 1-poly 6-metal n-well CMOS technology, and it consumes 307㎽ at 1.8V power supply.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.12
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• pp.1983-1993
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• 1993

A power-reduction technique for full-flash A/D converters is proposed. As the resolution of a full-flash A/D converter increases linearly, the number of comparators increases exponentially. The power dissipation is generally larger than other A/D converter architectures because there are many comparators, and they are operating continuously. In this proposed architecture, only a selected number of conmarators are made to operate instead of activating all the comparators of the full-flash A/D convertor. To determine whichcomparators should be activated, voltage levelfider circuits are used. A new clock driver is developed to suppress the dynamic glitch noise which is fed back into the input stage of the comparator. By using this clock driver, the glitch noise in the current source is reduced to one fourth of that when the typical clock signal is applied. The proposed architecture has been implemented with 1.2 m 5GHz BiCMOS technology. The maximum conversion speed is 350Msamples/s. and dissipates only 900mW.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.571-572
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• 2008

We propose a 4-bit 1.6GSample/s flash-A/D converter realized in a digital 0.18um 1-poly 4-metal CMOS technology. To achieve low power with good performance, we employ immanent C2MOS comparator scheme. The kickback noise is one of the most important issue in A/D comparator performance. To decrease the effect of kickback noise, here we introduce kickback neutralization technique. The designed A/D converter has an effective number of bits(ENOBs) of 3.93 while using 32mW operating at 1.6GHz.

• Journal of Convergence for Information Technology
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• v.11 no.9
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• pp.124-129
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• 2021

A time-interpolation technique has been applied to the conventional FLASH analog-to-digital converter (ADC) to increase a number of quantization level, thus it reduces not only a power dissipation, but also minimize an active chip area. In this work, we demonstrated 5-bit ADC which has 31 quantization levels consisting of 16 conventional voltage-mode comparators and 15 time-mode comparators. As a result, we have achieved about 48.4% voltage-mode comparator reductions. The ADC is fabricated in a 14nm fin Field-effect transistor (FinFET) process with an active die area of 0.0024 mm2 while consuming 0.82 mW through a 0.8 V supply. At 400-MS/s conversion rate, the ADC performs 28.03 dB SNDR (4.36 ENOB) at 21MHz input frequency.