• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.257-260
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• 1999

We have designed a 32-bit RISC microprocessor with 16/32-bit fixed-point DSP functionality. This processor, called YRD-5, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP and load/store instructions with one or more issue latency cycles. High performance was achieved with these parallel functional units while adopting a sophisticated 5-stage pipeline structure and an improved DSP unit.

• Proceedings of the KSPS conference
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• 2006.05a
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• pp.33-36
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• 2006

This paper describes a speech recognizer implemented on PDAs. The recognizer consists of feature extraction module, search module and utterance verification module. It can recognize 37 words that can be used in the telematics application and fixed-point operation is performed for real-time processing. Simulation results show that recognition accuracy is 94.5% for the in-vocabulary words and 56.8% for the out-of-task words.

• KIEE International Transaction on Electrical Machinery and Energy Conversion Systems
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• v.5B no.4
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• pp.374-381
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• 2005

The ability to provide quality power has become a significant issue in power systems. The main causes of poor power quality are harmonic currents, poor power factor, supply-voltage variations, etc. A technique of achieving both active current distortion compensation, power factor correction and also mitigating the supply-voltage variation (sag or swell) at the load side is presented in this paper. The operation and rating issues of the proposed Single-phase Unified Power Quality Conditioner are also highlighted. To reduce the total cost while simultaneously increasing the performance, the system is fully digitally controlled using the fixed-point TMS320F240 digital signal processor. The performances of the UPQC, which is composed by shunt and series PWM controlled-converters, have been verified on a laboratory prototype.

• Journal of The Korean Digital Architecture Interior Association
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• v.7 no.1
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• pp.35-42
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• 2007

Common residential environment is synthetic forms promote with organic organization of varied cultures and images. Users perceive and classify about these environments of feeling and atmosphere of each elements through their experiences and memories, not fixed point of view. In Korea, park designing of common residential room is in operation monotonously attach importance to economical efficiency without aesthetic structures, varied tries of materials, multiplicity, congruity of surrounding, and user-oriented plan. Recently, in policy of park designing has elements that obstruct to characteristic of environment because of applied to wrong guidelines which are end in investigation to model of an advanced countries'. In conclusion, this investigation shows improve on quality of park planning with the pivot of the matter is for users of common residential room. and park planning needs to multidimensional achieve.

• Proceedings of the IEEK Conference
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• 2002.07c
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• pp.2059-2062
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• 2002

For detection of digitally modulated signals, the receiver must be provide with accurate carrier phase and symbol timing estimates. So far, tots of algorithms have been suggested for those purposes. In general, a interpolation filter with TED(Timing Error Detection) like Gardner algorithm is popularly used for symbol timing estimate of digital communication receiver. Apart from the performance point of view, a multiplicative operation of any interpolation filter limits the symbol rate of the system. Hence, we suggest a new symbol timing estimate algorithm for high speed burst-mode fixed wireless communication system and analyze its performance in the AWGN channel.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.3
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• pp.82-90
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• 1998

A hit-miss transform(HMT) using synthetic structuring elements(SE's) for optical recognition of a moving target is proposed. A moving target which was obtained from a fixed view point has objects. In proposed HMT, SE's are synthesized by using SDF(synthetic discriminant function) algorithm for efficient recognitionof various shapes of true class objects in noisy and cluttered scene. The synthetic hit SE and the synthetic miss SE are composed of SDF of hit SE's and miss SE's for each true class object. Simulation results show the proposed method can be used for the recognition of various shapes of the true class with one one HMT operation.

• Journal of Power Electronics
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• v.13 no.6
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• pp.1016-1023
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• 2013

Predictive current control offers the potential for achieving more precise current control with a minimum of distortion and harmonic noise. However, the predictive method is difficult to implement and has a greater computational burden. This paper introduces a theoretical analysis and experimental verification for an improved predictive current control technique applied to single phase grid connected voltage source inverters (VSI). The proposed technique has simple calculations. An ATmega1280 microcontroller board is used to implement the proposed technique for a simpler and cheaper control system. To enhance the current performance and to obtain a minimum of current THD, an improved tri-level PWM switching strategy is proposed. The proposed switching strategy uses six operation modes instead of four as in the traditional strategy. Simulation results are presented to demonstrate the system performance with the improved switching strategy and its effect on current performance. The presented experimental results verify that the proposed technique can be implemented using fixed point 8-bit microcontroller to obtain excellent results.

• Journal of the Korean Institute of Telematics and Electronics
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• v.23 no.4
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• pp.429-438
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• 1986

In this paper we have designed and implemented a real-time, full-duplex SBC (sub-band coding) codec at 16kbps using a high speed digital signal processor, NEC 7720. The SBC codec employs a QMF(quadrature mirror filter) filter bank based on the tree structures of two-band analysis-synthesis pairs to partition speech signal into 4 octabe bands. Computer simulation has been done to investigate the effect of fixed-point computation of the NEC 7720. Three different performance measures, the conventional signal-to-noise ratio, the informal listening test, and an LPC(linear predictive coding)distance measure, have been used in this simulation. The necessary parameters have been optimized through the simulation. The developed hardware and software have been tested in real-time operation using a hardware emulator.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.1
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• pp.143-152
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• 2012

In this paper hardware implementation of GF($2^{191}$) elliptic curve cryptographic coprocessor which supports 7 operations such as scalar multiplication(kP), Menezes-Vanstone(MV) elliptic curve cipher/decipher algorithms, point addition(P+Q), point doubling(2P), finite-field multiplication/division is described. To meet structure resistant against simple power analysis, the ECC processor adopts the Montgomery scalar multiplication scheme which main loop operation consists of the key-independent operations. It has operational characteristics that arithmetic units, such GF_ALU, GF_MUL, and GF_DIV, which have 1, (m/8), and (m-1) fixed operation cycles in GF($2^m$), respectively, can be executed in parallel. The processor has about 68,000 gates and its simulated worst case delay time is about 7.8 ns under 0.35um CMOS technology. Because it has about 320 kbps cipher and 640 kbps rate and supports 7 finite-field operations, it can be efficiently applied to the various cryptographic and communication applications.