• Proceedings of the Acoustical Society of Korea Conference
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• 1998.08a
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• pp.121-126
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• 1998

고정 소수점 DSP 인 analog devices 사의 ADSP-2181을 이용하여 실시간 G.723.1 음성부호화기를 개발한 사례이다. G.723.1은 ITU에서 개발한 세계 표준 음성 부호화기로 낮은 전송율에서 고음질을 얻을 수 있다. 본 논문에서는 고정 소수점 DSP를 이용하여 부호화기를 갭라하는데 필요한 사항들을 제시하였다. 먼저 1절에서는 DAM성 부호화기의 특성에 대한 개괄을 설명하고, 2절에서는 G.723.1 부호화기의 특징을, 3절에서는 고정소수점 DSP를 이용하여 개발하는 과정을, 4절에서는 구현결과를 분석하였으며, 마지막으로 5절에서 결론을 맺는다.

• Journal of the Institute of Convergence Signal Processing
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• v.4 no.3
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• pp.7-14
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• 2003

MPEG-1 audio standard is the algorithm for the compression of high-qualify digital audio signals. The standard dictates the functions of encoder and decoder pair, and includes three different layers as the complexity and the performance of the encoder and decoder. In this paper, we implemented the real-time system of MPEG-1 audio layer III decoder(MP3) with the TMS320C541 fixed point DSP chip. MP3 algorithm uses psycho-acoustic characteristic of human hearing system, and it reduces the amount of data with eliminating the signals hard to be heard to the hearing system of human being. It is difficult to implement MP3 decoder with fixed Point DSP because of it's broad dynamic range. We implemented realtime system with fixed DSP chip by using weighted look-up tables to reduce the amount of calculation and solve the problem of broad dynamic range.

• Speech Sciences
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• v.10 no.2
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• pp.65-75
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• 2003

This paper describes the issues associated with the real-time implementation of G.723.1A dual-rate speech coder on a TMS320VC5402 DSP. Firstly, the main features of the G.723.1A speech coder and the procedure involved in the implementation using assembly and C languages are discussed. Various real-time implementation issues such as memory/MIPS tradeoffs are also presented. For fixed-point implementation, we converted the ITU-T fixed-point ANSI C code into TMS320VC5402 code in the bit-exact way through verification using the test vectors. Finally, as the result of implementation, we present the MIPS and memory requirement for the real-time operation.

• Proceedings of the IEEK Conference
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• 2000.11d
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• pp.119-122
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• 2000

Recently, many complex DSP (Digital Signal Processing) algorithms have being realized on RISC CPU due to good compilation, low power consumption and large memory space. But, real-time implementation of multiple DSP algorithms on RISC requires the minimum and efficient memory usage and the lower occupancy of CPU. In this thesis, the original floating-point code of MPEG-1 audio decoder is converted to the fixed-point code and then optimized to the efficient assembly code in time-consuming function in accord with RISC feature. Finally, compared with floating-point and fixed-point, about 30 and 3 times speed enhancements are achieved respectively. And 3~4 times memory spaces are spared.

• The Journal of the Acoustical Society of Korea
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• v.19 no.7
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• pp.42-47
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• 2000

This paper describes a real-time implementation of a GSM-EFR (Global System for Mobil communications Enhanced Full Rate) speech coder using OakDSP core; a 16bit fixed-point Digital Signal Processor (DSP) by DSP Group, Inc. The real-time implemented speech coder required about 24MIPS for computation and 7.06K words and 12.19K words for code and data memory, respectively. The implemented GSM-EFR speech coder passes all of test vectors provided by ETSI (European Telecommunication Standard Institute), and perceptual speech quality measurement using MNB algorithm shows that the quality of the GSM-EFR speech coder is similar to the one of 32kbps ADPCM. The real-time implemented GSM-EFR speech coder which is the highest bit-rate mode of the GSM-AMR speech coder will be used as the basic structure of the GSM-AMR speech coder which is embedded in MODEM ASIC of IMT2000 asynchronous mode mobile station.

• Journal of Advanced Navigation Technology
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• v.15 no.4
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• pp.591-595
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• 2011

In this paper, we design the hardware architecture of the BICM(Bit Interleaved Coded Modulation) module for next generation European broadcast system and implement the BICM module with DSP(Digital Signal Processor) TMS320C6474. Simulation result shows that the BER(Bit Error Rate) performance of the fixed-point BICM module using more than 8 bits is very similar to that of the floating-point BICM module.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1295-1297
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• 1996

CCITT G.721, G.723 standard ADPCM algorithm is implemented by using TI's fixed point DSP start kit (DSK). ADPCM can be implemented on a various rates, such as 16K, 24K, 32K and 40K. The ADPCM is sample based compression technique and its complexity is not so high as the other speech compression techniques such as CELP, VSELP and GSM, etc. ADPCM is widely applicable to most of the low cost speech compression application and they are tapeless answering machine, simultaneous voice and fax modem, digital phone, etc. TMS320C50 DSP is a low cost fixed point DSP chip and C50 DSK system has an AIC (analog interface chip) which operates as a single chip A/D and D/A converter with 14 bit resolution, C50 DSP chip with on-chip memory of 10K and RS232C interface module. ADPCM C code is compiled by TI C50 C-compiler and implemented on the DSK on-chip memory. Speech signal input is converted into 14 bit linear PCM data and encoded into ADPCM data and the data is sent to PC through RS232C. The ADPCM data on PC is received by the DSK through RS232C and then decoded to generate the 14 bit linear PCM data and converted into the speech signal. The DSK system has audio in/out jack and we can input and out the speech signal.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.57-60
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• 2005

The existing DSP for utility interactive photovoltaic generation system control, generally uses floating point process type. Because it is easy to use for number crunching, However it is too late and too expensive. fixed point process DSP, TMS320F2812, has high control speed and is rather inexpensive. This paper presents more efficient method for MPPT control using TMS320F2812.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.257-260
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• 1999

We have designed a 32-bit RISC microprocessor with 16/32-bit fixed-point DSP functionality. This processor, called YRD-5, combines both general-purpose microprocessor and digital signal processor (DSP) functionality using the reduced instruction set computer (RISC) design principles. It has functional units for arithmetic operation, digital signal processing (DSP) and memory access. They operate in parallel in order to remove stall cycles after DSP and load/store instructions with one or more issue latency cycles. High performance was achieved with these parallel functional units while adopting a sophisticated 5-stage pipeline structure and an improved DSP unit.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.409-413
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• 2008

In this paper, we introduce a platform of advanced multiple antenna system based on orthogonal frequency-division multiplexing (OFDM). The advanced multiple antennas have beamforming gain using array antenna. In array antenna systems, received signal has phase delay caused distance of each antennas, therefore it should compensate with optimum weight vector which calculated by Lagrange algorithm. To implement the presented above procedures using Digital Signal Processor (DSP), we should fixed-point design. The performance of implemented platform is verified through MATLAB$^{(R)}$ simulations with various signal environments.