• Journal of Korean Society of Industrial and Systems Engineering
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• v.30 no.1
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• pp.33-40
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• 2007

A multi-server queueing system with finite buffer is considered. The input flow is the BMAP (Batch Markovian Arrival Process). The service time has the PH (Phase) type distribution. Customers from the BMAP enter the system according to the discipline of partial admission. Besides ordinary (positive) customers, the Markovian flow (MAP) of negative customers arrives to the system. A negative customer can delete an ordinary customer in service if the state of its PH-service process belongs to some given set. In opposite case the ordinary customer is considered to be protected of the effect of negative customers. The stationary distribution and the main performance measures of the considered queueing system are calculated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.15 no.4
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• pp.324-330
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• 1990

In this paper, the hybrid ARQ system involving the single error correcting and double error detection (127, 119) cyclic Hamming codes and the SR(selective repeat) ARQ schemes with a finite receiver buffer has been designed and constructed. The system performance has been analyzed and simulated. As a result of the simulation, it has been shown that the transmitter retransmitted those data blocks that were detected in errors especially the request signal errors using two retransmission. The system performance was measured by throughput efficiency due to channel error effects.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.27 no.4
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• pp.15-22
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• 2004

본 논문의 목적은 유한 저장공간을 가지는 대기행렬 시스템에서 완전공유(Complete Sharing), 완전분할(Complete Partitioning), 최소할당공유(Sharing with Minimum Allocation)와 같은 다양한 저장공간 공유방안들을 비교ㆍ분석하는 것으로, 이를 위하여 먼저 각각의 공유방안에서의 대기행렬 안정상태확률을 효율적으로 구할 수 있는 방법이 제시되었다. 다음으로 각각의 저장공간 공유방안을 특징짓는데 필요한 몇 가지 성질들이 규명되었으며, 이를 토대로 각각의 저장공간 공유방안에 대하여 시스템 성능척도인 생산률들을 도출하는 한편, 이들의 대소관계를 파악하고, 수치실험을 통하여 이를 입증하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.11
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• pp.50-58
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• 2000

A Mach-Zehnder type $Ti:LiNbO_3$ optical modulator with a grooved $SiO_2$ buffer layer, was evaluated in terms of an electrode structure. The finite element method was performed to find out the optinum design parameters of electrodes. characteristic impedance ($Z_o$), MW effective index ($N_{eff}$) and attenuation constant ($a_o$)of fabricated traveling-wave electrodes were measured and compared with those obtained by the simulation expectation. For an optical modulator with 11${\mu}m$thick electrodes and a grooved $SiO_2$ buffer layer, the 3dB bandwidth based on the RF measurement results turned out to be 18GHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.103-106
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• 2012

A memory access method that data are read with different sequences with writing order is a simple but important procedure in many image compression standards, such as JPEG, MPEG1/2/4, H.264, and HEVC. For real time processing, double buffering is widely used using two block sized buffers, that accesses buffers concurrently with alternative way to read and write. In some cases like a transpose memory in 2D DCT with a simple and regular access order, a single buffering which requires only single block sized buffer can be used. This paper shows that even in complex access orders there is a regularity among updating orders within a finite turns, and suggested an effective implementation method using a single block sized buffer to process concurrent read/write operation with different access orders.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.7
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• pp.1321-1334
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• 1994

This paper presents the service handling schemes of an intelligent peripheral(IP) which provides the service function as a physical entity in the intelligent network. Four service request handling scheme are compared for and IP which can handle both ordinary requests and prioritized requests on the blocked-call-delayed basis. Delayed requests are assumed to be stored in a finite storage buffer. Scheme-I exclusively allows prioritized requests be stored and to use a fixed number of reserved servers. The other three schemes without reserved servers(Scheme-II.III,and IV) allow both types of requests to be stored and prioritized requests pushout ordinary requests if the buffer is full. For these four schemes, the blocking probabilities and delay distributions of both types of requests are numerically obtained. From the numericall results, the schemes without reserved servers reduce the blocking probability of ordinary requists without a severe penalty on proritized requests. For three schemes without reserved servers, it is noted that prioritized requests should br served on the first-in, first-out basis, and ordinary requests should be served on the last-in, first-out basis.

• The Transactions of the Korea Information Processing Society
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• v.7 no.8
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• pp.2484-2496
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• 2000

High speed switches have been developing to interconnect a large number of nodes. It is important to analyze the switch performance under various conditions to satisfy the requirements. Queueing analysis, in general, has the intrinsic problem of large state space dimension and complex computation. In fact, The petri net is a graphical and mathematical model. It is suitable for various applications, in particular, manufacturing systems. It can deal with parallelism, concurrence, deadlock avoidance, and asynchronism. Currently it has been applied to the performance of computer networks and protocol verifications. This paper presents a framework for modeling and analyzing ATM switch using stochastic activity networks (SANs). In this paper, we provide the ATM switch model using SANs to extend easily and an approximate analysis method to apply A TM switch models, which significantly reduce the complexity of the model solution. Cell arrival process in output-buffered Queueing A TM switch with finite buffer is modeled as Markov Modulated Poisson Process (MMPP), which is able to accurately represent real traffic and capture the characteristics of bursty traffic. We analyze the performance of the switch in terms of cell-loss ratio (CLR), mean Queue length and mean delay time. We show that the SAN model is very useful in A TM switch model in that the gates have the capability of implementing of scheduling algorithm.

• Journal of KIISE:Computer Systems and Theory
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• v.26 no.7
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• pp.847-862
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• 1999

본 논문에서는 유한버퍼의(finite-buffered) 동기화된(synchronous) 큐잉모델(queueing model)을 이용하여 명령어들간의 병렬성, 분기명령의 빈도수, 분기예측(branch prediction)의 정확도, 캐쉬미스 등의 파라미터들을 고려하여 프로세서의 명령어 실행율을 예측하며 캐쉬의 성능과 파이프라인 성능간의 관계를 분석할 수 있는 새로운 해석적 모델을 제안하였다. 해석적 모델은 모델의 타당성을 검증하기 위해서 시뮬레이션을 수행하여 얻은 결과와 비교하였다. 해석적 모델과 시뮬레이션을 비교한 결과 대부분 10% 오차 내에서 일치하였다. 본 연구를 통하여 얻은 해석적 모델을 사용하면 시뮬레이션에서는 드러나지 않는 성능제약의 원인에 대한 명확한 규명이 가능하기 때문에 성능향상을 위한 설계자료를 얻을 수 있으며, 시스템 성능 밸런스를 위한 캐쉬와 비순차이슈 파이프라인 성능간의 관계에 대한 정확한 분석이 가능하다.Abstract This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc.. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error compared to simulation results. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.

• Journal of computational fluids engineering
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• v.9 no.1
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• pp.1-9
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• 2004

Large eddy simulation is used to investigate the compressible flow over a cavity with high aspect ratio. The sub-grid scale stresses are modeled using the dynamic model. The compressible Navier-Stokes equations are solved with the sixth order accurate compact finite difference scheme in the space and the 4th order Runge-Kutta scheme in the time. The buffer Bone techniques are used for non-reflecting boundary conditions. The results show the shear layer oscillation over the cavity. The votical disturbances, the roll-up of vorticity, and impingement and scattering of vorticity at the downstream cavity edge can be seen in the shear layer. Several peaks for the resonant frequencies are found in the spectra of the vertical velocity at the center-line. The most energetic Peak near the downstream edge is different from that at the center part of the cavity The pressure has its minimum value in the vortex core inside the cavity, and becomes very high at the downstream face of the cavity. The variation of the model coefficient predicted by the dynamic model is quite large between 0 and 0.3. The model coefficient increases in the stream-wise evolution of the shear layer and sharply decreases near the wall due to the wall effect.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.2 no.4
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• pp.583-592
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• 1998

In this paper, the cell loss rate is analyzed in terms of the input traffic stream of different speed in ATM network. The cell loss rate is calculated by birth-death process of Leaky-Bucket mechanism as the representative algorithm of usage parameter control. The cell loss rate assumed 2-state MMPP input process to be birth-death process by considering the character of token pool about finite capacity queue. The results from numerical analysis show that the cell loss rate decreases abruptly according to the buffer size increase. The computer simulation by SIMSCRIPT II.5 has been done and compared with on/off input source case to verify the analysis results.