• JSTS:Journal of Semiconductor Technology and Science
• /
• v.3 no.4
• /
• pp.181-187
• /
• 2003

This paper presents an 125MHz, 128-phase phase-locked loop using interpolation technique for digital timing recovery. To reduce the power consumption and chip area, phase interpolation was performed over only selected windows, instead of overall period. Four clocks were used for phase interpolation to avoid the output jitter increase due to the interpolation clock (clock used for phase interpolation) switching. Also, the output clock was fed back to finite-state machine (FSM) where the multiplexer selection signals are generated to eliminate the possible output glitches. The PLL implemented in a $0.25\mu\textrm{m}$ CMOS process and dissipates 80mW at 2.5V supply and occupies $0.84\textrm{mm}^2.

• Proceedings of the Korean Society of Broadcast Engineers Conference
• /
• 2009.01a
• /
• pp.128-135
• /
• 2009

In this paper, we proposed an interactive GUI (Graphical User Interface) system to model buildings with an editable script. Our system also provides probabilistic finite-state machine (PFSM) to define the relationships of sub-models with transformation matrices and transition probabilities for constructing new novel building models automatically. User can not only get various building models by PFSM but also adjust the probabilities of sub-models from PFSM to get desired building models. As shown in the results, the various and vivid building models can be constructed easily and quickly for non-expert users. Besides, user can also edit the script file which is provided by our system to modify the properties directly.

• Proceedings of the KIEE Conference
• /
• 2000.11b
• /
• pp.336-338
• /
• 2000

Recently many studies have been performed for variable speed control of induction motor. Direct Torque Control(DTC) is emerging technique for variable speed control of PWM inverter driven induction motor. DTC allows the direct control of stator flux and instantaneous torque through simple algorithm. In this paper ASIC design technique using VHDL is applied to DTC based speed control of induction motor. ASIC for DTC based speed control is designed through the description of coordinate transformation, speed controller stator flux and torque estimator, stator flux and torque controller, stator flux position detector. FSM(Finite State Machine) and inverter voltage switching vector. Finally the above system has been implemented on the FPGA (XC4052XL-PG411). Simulation and experiment has been performed to verify the performance of the designed ASTC.

• Journal of Korea Society of Industrial Information Systems
• /
• v.16 no.2
• /
• pp.85-97
• /
• 2011

Wireless sensor networks have emerged as one of the key enabling technologies for ubiquitous computing since wireless intelligent sensor nodes connected by short range communication media serve as a smart intermediary between physical objects and people in ubiquitous computing environment. We recognize the wireless sensor network as a massively distributed and deeply embedded system. Such systems require concurrent and asynchronous event handling as a distributed system and resource-consciousness as an embedded system. Since the operating environment and architecture of wireless sensor networks, with the seemingly conflicting requirements, poses unique design challenges and constraints to developers, we propose a very new operating system for sensor nodes based on finite state machine. In this paper, we clarify the design goals reflected from the characteristics of sensor networks, and then present the heart of the design and implementation of a compact and efficient state-driven operating system, SenOS. We describe how SenOS can operate in an extremely resource constrained sensor node while providing the required reactivity and dynamic reconfigurability with low update cost. We also compare our experimental results after executing some benchmark programs on SenOS with those on TinyOS.

• Journal of the Korea Society of Computer and Information
• /
• v.12 no.6
• /
• pp.21-30
• /
• 2007

Simulation means modeling structures or behaviors of the various objects, and experimenting them on the computer system. And the major approaches are DEVS(Discrete Event Systems Specification). Petri-net or Automata and so on. But, the simulation problems are getting more complex or complicated these days, so that an intelligent agent-based is being studied. In this paper, we are describing an intelligent agent-based simulation tool, which can supports the simulation experiment more efficiently. The significances of our system can be described as follows. First, the system can provide some AI algorithms through the system libraries. Second, the system supports simple method of designing the simulation model, since it's been built under the Finite State Machine (FSM) structure. And finally, the system acts as a simulation framework by supporting user not only the simulation engine, but also user-friendly tools, such as modeler scriptor and simulator. The system mainly consists of main simulation engine, utility tools, and some other assist tools, and it is tested and showed some efficient results in the three different problems.

• The Journal of Korean Institute of Communications and Information Sciences
• /
• v.33 no.6B
• /
• pp.456-468
• /
• 2008

In this paper, we design Input/Output modules as a preference work for implementation of hybrid two stage AWG based WDM-PON and verify operations of each function modules through the logic simulation. This WDM-PON system provides service to 128 ONUs through 32 wavelength and one wavelength is shared for upstream transmission with four ONU while each wavelength is allocated to each ONU for downstream transmission. The designed WDM-PON MAC chip is based on sub-MAC which consists of one control unit and reception unit and four transmission unit. To design the reception and transmission unit of sub-MAC, we define the functions of the sub-MAC, pins of the modules, control signal and timing of each signal. We intend to design MAC chip with 1Gbps transmission rate. Thus the designed MAC chip is worked on 125MHz clock rate. We define FSM and design Input/Output modules with VHDL. The logic simulation of the modules is executed by the ModelSIM simulator.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.15 no.2
• /
• pp.439-446
• /
• 2011

In this paper, we proposed and implemented a dedicated hardware for Huffman coding which is a method of entropy coding to use compressing multimedia data with video coding. The proposed Huffman codec consists Huffman encoder and decoder. The Huffman encoder converts symbols to Huffman codes using look-up table. The Huffman code which has a variable length is packetized to a data format with 32 bits in data packeting block and then sequentially output in unit of a frame. The Huffman decoder converts serial bitstream to original symbols without buffering using FSM(finite state machine) which has a tree structure. The proposed hardware has a flexible operational property to program encoding and decoding hardware, so it can operate various Huffman coding. The implemented hardware was implemented in Cyclone III FPGA of Altera Inc., and it uses 3725 LUTs in the operational frequency of 365MHz

• MALSORI
• /
• no.50
• /
• pp.51-69
• /
• 2004

In this paper, we present a one-pass semi-dynamic network decoding framework that inherits both advantages of fast decoding speed from static network decoders and memory efficiency from dynamic network decoders. Our method is based on the novel language model network representation that is essentially of finite state machine (FSM). The static network derived from the language model network [1][2] is partitioned into smaller subnetworks which are static by nature or self-structured. The whole network is dynamically managed so that those subnetworks required for decoding are cached in memory. The network is near-minimized by applying the tail-sharing algorithm. Our decoder is evaluated on the 25k-word Korean broadcast news transcription task. In case of the search network itself, the network is reduced by 73.4% from the tail-sharing algorithm. Compared with the equivalent static network decoder, the semi-dynamic network decoder has increased at most 6% in decoding time while it can be flexibly adapted to the various memory configurations, giving the minimal usage of 37.6% of the complete network size.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.51 no.1
• /
• pp.79-89
• /
• 2014

It has been an increase in consumers who want a high-capacity and fast speed by the newly diffused mobile device(Smart phones, Ultra books, Tablet PC). As a result, the demand for Flash Memory is constantly increasing. Flash Memory is separated by a NAND-type and NOR-type. NAND-type Flash Memory speed is slow, but price is cheaper than the NOR-type Flash Memory. For this reason, NAND-type Flash Memory is widely used in the mobile market. So Fault Detection is very important for Flash Memory Test. In this paper, Proposed PMBIST for Pattern Test of NAND-type Flash Memory improved Fault detection.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.11 no.6
• /
• pp.2207-2213
• /
• 2010

A new scheme for variable structure control design which is based on eigenvalues assignment of sliding mode is developed. In conventional methods, generally, specific type of system matrix like canonical or regular form is required to construct a switching surface. Furthermore, the methods are not explicit. The new method in this paper solved the problems. No special type of system matrix is required and very explicit. It is shown that the switching surface can be constructed and determined uniquely without any dependency on the system form. The proposed method is based on the fact that the dynamics of sliding mode is determined by system zeros. Finally, a numerical example is given to verify the validity of the results studied in this paper.