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http://dx.doi.org/10.6109/jkiice.2011.15.2.439

VLSI Architecture of High Performance Huffman Codec  

Choi, Hyun-Jun (안양대학교)
Seo, Young-Ho (광운대학교)
Kim, Dong-Wook (광운대학교)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.15, no.2, 2011 , pp. 439-446 More about this Journal
Abstract
In this paper, we proposed and implemented a dedicated hardware for Huffman coding which is a method of entropy coding to use compressing multimedia data with video coding. The proposed Huffman codec consists Huffman encoder and decoder. The Huffman encoder converts symbols to Huffman codes using look-up table. The Huffman code which has a variable length is packetized to a data format with 32 bits in data packeting block and then sequentially output in unit of a frame. The Huffman decoder converts serial bitstream to original symbols without buffering using FSM(finite state machine) which has a tree structure. The proposed hardware has a flexible operational property to program encoding and decoding hardware, so it can operate various Huffman coding. The implemented hardware was implemented in Cyclone III FPGA of Altera Inc., and it uses 3725 LUTs in the operational frequency of 365MHz
Keywords
huffman code; encoder; FPGA; VLSI; video coding; codec;
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