• Journal of the Korean Crystal Growth and Crystal Technology
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• v.10 no.3
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• pp.199-204
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• 2000

In this study, the ZnS nanosized thin films that could be used for fabrication of blue light-emitting diodes, electro-optic modulators, and n-window layers of solar cells were grown by the solution growth technique (SGT), and their structural and optical properties were examined. Based on these results, the quantum size effects of ZnS were systematically investigated. Governing factors related to the growth condition were the concentration of precursor solution, growth temperature, concentration of aq. ammonia, and growth duration. X-ray diffraction patterns showed that the ZnS thin film obtained in this study had the cubic structure ($\beta$-ZnS). When the growth temperature was $75^{\circ}C$, the surface morphology and the grain size uniformity were the best. The energy band gaps of samples were determined from the optical transmittance valued, and were shown to vary from 3.69 eV to 3.91 eV. These values were substantially higher than 3.65 eV of bulk ZnS, demonstrating that the quantum size effect of SGT grown ZnS is remarkable. Photoluminescence (PL) peaks were observed at the positions corresponding to the lower energy than that to energy band gap, illustrating that the surface states were induced by the ultra-fineness of grains in ZnS films. Particularly, for the first time, it is reported for the SGT grown ZnS that the PL peaks were shifted depending on the grain size.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.17 no.5
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• pp.179-186
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• 2007

Single crystal $CdGa_2Se_4$ layers were grown on a thoroughly etched semi-insulating GaAs(100) substrate at $420^{\circ}C$ with the hot wall epitaxy(HWE) system by evaporating the polycrystal source of $CdGa_2Se_4$ at $630^{\circ}C$. The crystalline structure of the single crystal thin films was investigated by the photoluminescence and double crystal X-ray diffraction(DCXD). The carrier density and mobility of single crystal $CdGa_2Se_4$ thin films measured with Hall effect by van der Pauw method are $8.27{\times}10^{17}cm^{-3},\;345cm^2/V{\cdot}s$ at 293 K, respectively. The photocurrent and the absorption spectra of $CdGa_2Se_4/SI$(Semi-Insulated) GaAs(100) are measured ranging from 293 K to 10 K. The temperature dependence of the energy band gap of the $CdGa_2Se_4$ obtained from the absorption spectra was well described by the Varshni's relation $E_g(T)=2.6400eV-(7.721{\times}10^{-4}eV/K)T^2/(T+399K)$. Using the photocurrent spectra and the Hopfield quasicubic model, the crystal field energy(${\Delta}cr$) and the spin-orbit splitting energy(${\Delta}so$) far the valence band of the $CdGa_2Se_4$ have been estimated to be 106.5 meV and 418.9 meV at 10 K, respectively. The three photocurrent peaks observed at 10 K are ascribed to the $A_{1^-},\;B_{1^-},\;and\;C_{11}-exciton$ peaks.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.21 no.4
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• pp.362-370
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• 2010

In this paper, a compact RF Front-end module for Wireless Fidelity(Wi-Fi) and Worldwide Interoperability for Microwave Access(WiMAX) applications is realized by low temperature co-fired ceramic(LTCC) technology. The RF Front-end module is composed of three LTCC band-pass filters, a Film Bulk Acoustic Resonator(FBAR) filter, fully embedded matching circuits, an SPDT switch for mode selection, an SPDT switch for Tx/Rx selection, and an SP4T switch for band selection. The parasitic elements of 0.2~0.3 pF are generated by the structure of stacking in the top pad pattern for DC block capacitor of SPDT switch for mode selection. These kinds of parasitic elements break the matching characteristic, and thus, the overall electrical performance of the module is degraded. In order to compensate it, we insert a parallel lumped-element inductor on capacitor pad pattern for DC block, so that we obtain the optimized performance of the RF Front-end module. The fabricated RF front-end module has 12 layers including three inner grounds and it occupies less than $6.0mm{\times}6.0mm{\times}0.728mm$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.6
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• pp.646-651
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• 2018

This paper reports that the electronic properties at a $P3HT/TiO_2$ interface associated with exciton dissociation and transport can be tailored by the insertion of a graphene quantum dot (GQD) layer. For donor/acceptor interface modification in an $ITO/TiO_2/P3HT/Al$ photovoltaic (PV) device, a continuous GQD film was prepared by a sonication treatment in solution that simplifies the conventional processes, including laser fragmentation and hydrothermal treatment, which limits a variety of component layers and involves low cost processing. The high conductivity and favorable energy alignment for exciton dissociation of the GQD layer increased the fill factor and short circuit current. The origin of the improved parameters is discussed in terms of the broad light absorption and enhanced interfacial carrier transport.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.297-297
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• 2010

Precise control of the position and density of doping elements at the nanoscale is becoming a central issue for realizing state-of-the-art silicon-based optoelectronic devices. As dimensions are scaled down to take benefits from the quantum confinement effect, however, the presence of interfaces and the nature of materials adjacent to silicon turn out to be important and govern the physical properties. Utilization of visible light is a promising method to overcome the efficiency limit of the crystalline Si solar cells. Si quantum dots (QDs) have been proposed as an emission source of visible light, which is based on the quantum confinement effect. Light emission in the visible wavelength has been reported by controlling the size and density of Si QDs embedded within various types of insulating matrix. For the realization of all-Si QD solar cells with homojunctions, it is prerequisite not only to optimize the impurity doping for both p- and n-type Si QDs, but also to construct p-n homojunctions between them. In this study, XPS and SIMS were used for the development of p-type and n-type Si quantum dot solar cells. The stoichiometry of SiOx layers were controlled by in-situ XPS analysis and the concentration of B and P by SIMS for the activated doping in Si nano structures. Especially, it has been experimentally evidenced that boron atoms in silicon nanostructures confined in SiO2 matrix can segregate into the Si/$SiO_2$ interfaces and the Si bulk forming a distinct bimodal spatial distribution. By performing quantitative analysis and theoretical modelling, it has been found that boron incorporated into the four-fold Si crystal lattice can have electrical activity. Based on these findings, p-type Si quantum dot solar cell with the energy-conversion efficiency of 10.2% was realized from a [B-doped $SiO_{1.2}$(2 nm)/$SiO_2(2\;nm)]^{25}$ superlattice film with a B doping level of $4.0{\times}10^{20}\;atoms/cm^2$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.14 no.4
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• pp.2037-2042
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• 2013

A TCO-less palladium (Pd) catalytic layer on the glass substrate was assessed as the counter electrode (CE) in a dye sensitized solar cell (DSSC) to confirm the stability of Pd with the $I^-/I_3{^-}$electrolyte on the DSSC performance. A 90nm-thick Pd film was deposited by a thermal evaporator. Finally, DSSC devices of $0.45cm^2$ with glass/FTO/blocking layer/$TiO_2$/dye/electrolyte(10 mM LiI + 1 mM $I_2$ + 0.1 M $LiClO_4$ in acetonitrile solution)/Pd/glass structure was prepared. We investigated the microstructure and photovoltaic property at 1 and 12 hours after the sample preparation. The optical microscopy, field emission scanning electron microscopy (FESEM), cyclic voltammetry measurement (C-V), and current voltage (I-V) were employed to measure the microstructure and photovoltaic property evolution. Microstructure analysis showed that the corrosion by reaction between the Pd layer and the electrolyte occurred as time went by, which led the decrease of the catalytic activity and the efficiency. I-V result revealed that the energy conversion efficiency after 1 and 12 hours was 0.34% and 0.15%, respectively. Our results implied that we might employ the other non-$I^-/I_3{^-}$electrolyte or the other catalytic metal layers to guarantee the long term stability of the DSSC devices.

• Cartoon and Animation Studies
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• s.45
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• pp.479-512
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• 2016

This is a practice-based research, aiming to explore the experiments of Animated Documentary, which is a unique form can explore the mysteries and complexity of memories. Animated Documentary is a medium through which one can reveal an individual's memories within the context of a narrative that is historically situated and influenced. The marriage of animation and documentary gave birth to a new form of film. How to category this new form? Is it an animated short or documentary short? In fact, this raises issue that questioning the nature of animation and documentary. From Shuibo Wang's works, more young Chinese artists began to experiment with symbols (related to the Political Pop Trend) in visual narration, which could also be seen as a reflection of structuralism and semiology in the contemporary Chinese art field. As a case study, this paper demonstrates how animated short "Ketchup" revealed the problems of youth and social turmoil through the memories of a six-year boy. On the Festivals and conferences, the publics were shocked to know "Ketchup" based on true memories, and they were more curious why the crucial things almost be forgotten. Actually forget fulness is one of the layers of memories and Animated Documentary will offer a new way to explore how our memories are shaped.

• Journal of the Korean Vacuum Society
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• v.22 no.2
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• pp.98-104
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• 2013

$VO_2$ is an attractive thermochromic material, in which its electrical and optical properties can be switched by the structural phase-transition about $68^{\circ}C$. Recently, graphene is also a rising material which is researched as a transparent electrode because of its superior electrical and optical characteristics. In this respect, we try to fabricate the hybridized films using $VO_2$ and graphene on transparent sapphire substrate and then we investigate a structure and characterize an optical property for the samples as a function of temperature. According to the result of IR-transmittance analysis of $VO_2$ films as a function of temperature, the graphene-supported sapphire substrates are better about 10% than the bare sapphire substrates. The mean phase transition temperatures are also decreased as the number of graphene-layers increased and the hysteresis of phase transitions are narrowed.

• Proceedings of the Korean Vacuum Society Conference
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• 2011.02a
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• pp.134-134
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• 2011

High-k dielectric materials such as $HfO_2$, $ZrO_2$ and $Al_2O_3$ increase gate capacitance and reduce gate leakage current in MOSFET structures. This behavior suggests that high-k materials will be promise candidates to substitute as a tunnel barrier. Furthermore, stack structure of low-k and high-k tunnel barrier named variable oxide thickness (VARIOT) is more efficient.[1] In this study, we fabricated the $WSi_2$ nanocrystals nonvolatile memory device with $SiO_2/HfO_2/Al_2O_3$ tunnel layer. The $WSi_2$ nano-floating gate capacitors were fabricated on p-type Si (100) wafers. After wafer cleaning, the phosphorus in-situ doped poly-Si layer with a thickness of 100 nm was deposited on isolated active region to confine source and drain. Then, on the gate region defined by using reactive ion etching, the barrier engineered multi-stack tunnel layers of $SiO_2/HfO_2/Al_2O_3$ (2 nm/1 nm/3 nm) were deposited the gate region on Si substrate by using atomic layer deposition. To fabricate $WSi_2$ nanocrystals, the ultrathin $WSi_2$ film with a thickness of 3-4 nm was deposited on the multi-stack tunnel layer by using direct current magnetron sputtering system [2]. Subsequently, the first post annealing process was carried out at $900^{\circ}C$ for 1 min by using rapid thermal annealing system in nitrogen gas ambient. The 15-nm-thick $SiO_2$ control layer was deposited by using ultra-high vacuum magnetron sputtering. For $SiO_2$ layer density, the second post annealing process was carried out at $900^{\circ}C$ for 30 seconds by using rapid thermal annealing system in nitrogen gas ambient. The aluminum gate electrodes of 200-nm thickness were formed by thermal evaporation. The electrical properties of devices were measured by using a HP 4156A precision semiconductor parameter analyzer with HP 41501A pulse generator, an Agillent 81104A 80MHz pulse/pattern generator and an Agillent E5250A low leakage switch mainframe. We will discuss the electrical properties for application next generation non-volatile memory device.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.