• Journal of Power Electronics
• /
• 제18권5호
• /
• pp.1523-1535
• /
• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• 로봇학회논문지
• /
• 제4권1호
• /
• pp.1-9
• /
• 2009

Radio Frequency Identification (RFID) is an automatic identification method. Information such as identification, logistics history, and specification of products are written and stored into the memory of RFID tags (that is, transponders), and retrieved through RF communication between RFID reader device and RFID tags. RFID systems have been applied to many fields of transportation, industry, logistics, environment, etc in order to improve business efficiency and reduce maintenance cost as well. Recently, some research results are announced in which RFID devices are combined with other sensors for mobile robot localization. In this paper, design of multi-protocol baseband for RFID reader device is proposed, and the baseband modem is implemented into SoC (System On a Chip). The baseband modem SoC for multi-protocol RFID reader is composed of several IP (Intellectual Property) blocks such as multi-protocol blocks, CPU, UART(Universal Asynchronous Receiver and Transmitter), memory, etc. As a result, the SoC implemented with FPGA(Field Programmable Gate Array) is applied to real product. It is shown that the size of RFID Reader module designed with the FPGA becomes smaller, and the SoC chip price for the same function becomes cheap. In addition, operation performance could be the same or better than that of the product with no SoC applied.

• 한국통신학회논문지
• /
• 제31권1C호
• /
• pp.20-25
• /
• 2006

본 논문에서는 Tree-LDPC 코드의 성능을 scaling 인자를 이용한 min-sum 알고리즘을 사용하여 나타내고, 그때의 water fall 영역에서의 접근 성능은 density evolution 기법을 사용하여 나타낸다. Density evolution 기법을 통하여 얻어진 최적의 scaling 인자를 사용하게 되면 min-sum 알고리즘을 사용하는 Tree-LDPC 코드는 sum-product 알고리즘을 사용했을 때와 비슷한 성능을 나타낼 정도로 상당한 성능 이득을 갖게 되는 반면 sum-product 알고리즘을 사용했을 때보다 복호 복잡도가 훨씬 줄어들게 된다. 작은 인터리버 크기를 갖는 Tree-LDPC 복호기를 FPGA(Field Programmable Gate Array)로 구현하였다.

• 대한전기학회논문지:전력기술부문A
• /
• 제53권7호
• /
• pp.365-374
• /
• 2004

The relay measures the frequency of the power system in order to detect faults and separate them from the system. Many estimation algorithms for the relay have been proposed to accurately measure the frequency. This paper proposes a new frequency measurement method using the digital phase locked-loop(DPLL) for the relay of the power system. The proposed method is configured with a DPLL scheme and verified through computer simulations and experimental tests. In order to cope with noises in the power system, filters are included in the input signal processing part and the frequency comparator. MATLAB is used for computer simulations and an experimental setup with a CPU and an FPGA(Field Programmable Gate Array) is constructed. The loop filter of the DPLL is run in the CPU software In adjust parameters and others are in the FPGA. Experimental tests are performed lot a function generator and the power system. Results show that the proposed method is appropriate to the frequency measurement for the relay.

• 대한전자공학회논문지TE
• /
• 제37권5호
• /
• pp.93-102
• /
• 2000

본 논문은 DAMA-SCPC 위성통신 시스템의 디지털 모뎀의 기능 및 성능 규격들을 제시하고, 제시한 규격을 만족하는 위성모뎀의 구조 설계 및 구현에 대하여 기술한다. 다양하면서 융통성이 요구되는 위성모뎀의 규격들을 만족시키기 위하여 디지털 신호 처리기(DSP)와 프로그래머블 게이트 어레이(FPGA)를 기반으로 하여 설계 및 구현되었다. 구현된 위성모뎀은 DAMA-SCPC 위성통신 시스템에 통합하여 수행한 시험에서 안정된 동작과 제시된 기능 및 성능 규격을 모두 만족함을 검증하였다. 연속모드(at Eb/No=4.7, FEC=3/4) 에서 측정된 BER은 약 1×10E-4의 성능을 보여 주었다.

• Journal of information and communication convergence engineering
• /
• 제18권1호
• /
• pp.1-7
• /
• 2020

This paper proposes a fast-processing and low-cost hardware multiple input multiple output (MIMO) channel emulator. The channel emulator is an important component of hardware-based simulation systems. The novelty of this work is the use of sharing and pipelining functions to reduce hardware resource utilization while maintaining a high sample rate. In our proposed emulator, the samples are created sequentially and interpolated to ensure the sample rate is equal to the base band rate. The proposed 4 × 4 MIMO requires low-cost hardware resource so that it can be implemented on a single field-programmable gate array (FPGA) chip. An implementation on Xilinx Virtex-7 VX980T was found to occupy 10.47% of the available configurable slice registers and 12.58% of the FPGA's slice lookup tables. The maximum frequency of the proposed emulator is 758.064 MHz, so up to 560 different paths can be processed simultaneously to generate 560 × 758 million × 2 × 32 bit complex-valued fading samples per second.

• Journal of Power Electronics
• /
• 제11권4호
• /
• pp.542-550
• /
• 2011

This paper describes the design and hardware implementation of a Single Input Fuzzy Logic Controller (SIFLC) to regulate the output voltage of a boost power converter. The proposed controller is derived from the signed distance method, which reduces a multi-input conventional Fuzzy Logic Controller (CFLC) to a single input FLC. This allows the rule table to be approximated to a one-dimensional piecewise linear control surface. A MATLAB simulation demonstrated that the performance of a boost converter is identical when subjected to the SIFLC or a CFLC. However, the SIFLC requires nearly an order of magnitude less time to execute its algorithm. Therefore the former can replace the latter with no significant degradation in performance. To validate the feasibility of the SIFLC, a 50W boost converter prototype is built. The SIFLC algorithm is implemented using an Altera FPGA. It was found that the SIFLC with asymmetrical membership functions exhibits an excellent response to load and input reference changes.

• 전기학회논문지P
• /
• 제67권1호
• /
• pp.9-14
• /
• 2018

In this paper, we introduce an AES-based security chip for the embedded system of Internet of Things(IoT). We used Verilog HDL to implement the AES algorithm in FPGA. The designed AES module creates 128-bit cipher by encrypting 128-bit plain text and vice versa. RTL simulations are performed to verify the AES function and the theory is compared to the results. An FPGA emulation was also performed with 40 types of test sequences using two Altera DE0-Nano-SoC boards. To evaluate the performance of security algorithms, we compared them with AES implemented by software. The processing cycle per data unit of hardware implementation is 3.9 to 7.7 times faster than software implementation. However, there is a possibility that the processing speed grow slower due to the feature of the hardware design. This can be solved by using a pipelined scheme that divides the propagation delay time or by using an ASIC design method. In addition to the AES algorithm designed in this paper, various algorithms such as IPSec can be implemented in hardware. If hardware IP design is set in advance, future IoT applications will be able to improve security strength without time difficulties.

• 한국지능시스템학회논문지
• /
• 제21권5호
• /
• pp.595-601
• /
• 2011

본 논문에서는 영상 정보를 이용하여 로보커 팔위의 역진자의 밸런싱 제어를 한다. 로봇 팔위에 놓인 역진자의 각도는 카메라로 검출하고 검출된 각도 값은 제어기로 귀환되어 오차를 생성한다. 따라서 전체 제어루프는 폐회로 루프를 형성한다. 제어 성능을 높이기 위해 기존 선형제어기에 신경망 제어기를 더하였다. RBF 네트워크의 학습 알고리즘은 FPGA에 설계된 부동소수점 연산이 가능한 디지털 제어기에 의해 수행된다. 실험을 통하여 전체 시스템 성능을 검증하였다.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -3
• /
• pp.1567-1570
• /
• 2002

This paper deals with FPGA(Field Programmable Gate Array) implementation of the AAC(Advanced Audio Coding) decoder. On modern computer culture, according to the high quality data is required in multimedia systems area such as CD, DAT(Digital Audio Tape) and modem. So, the technology of data compression far data transmission is necessity now. MPEG(Moving Picture Experts Group) would be a standard of those technology. MPEG-2 AAC is the availableness and ITU-R advanced coding scheme far high quality audio coding. This MPEG-2 AAC audio standard allows ITU-R 'indistinguishable' quality according to at data rates of 320 Kbit/sec for five full-bandwidth channel audio signals. The compression ratio is around a factor of 1.4 better compared to MPEG Layer-III, it gets the same quality at 70％ of the titrate. In this paper, for a real time processing MPEG2 AAC decoding, it is implemented on FPGA chip. The architecture designed is composed of general DSP(Digital Signal Processor). And the Processor designed is coded using VHDL language. The verification is operated with the simulator of C language programmed and ECAD tool.