• Journal of the Korean Society of Systems Engineering
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• v.14 no.2
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• pp.73-82
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• 2018

In this work, a hardware based cryptographic module for the cyber security of nuclear power plant is developed using a system engineering approach. Nuclear power plants are isolated from the Internet, but as shown in the case of Iran, Man-in-the-middle attacks (MITM) could be a threat to the safety of the nuclear facilities. This FPGA-based module does not have an operating system and it provides protection as a firewall and mitigates the cyber threats. The encryption equipment consists of an encryption module, a decryption module, and interfaces for communication between modules and systems. The Advanced Encryption Standard (AES)-128, which is formally approved as top level by U.S. National Security Agency for cryptographic algorithms, is adopted. The development of the cyber security module is implemented in two main phases: reverse engineering and re-engineering. In the reverse engineering phase, the cyber security plan and system requirements are analyzed, and the AES algorithm is decomposed into functional units. In the re-engineering phase, we model the logical architecture using Vitech CORE9 software and simulate it with the Enhanced Functional Flow Block Diagram (EFFBD), which confirms the performance improvements of the hardware-based cryptographic module as compared to software based cryptography. Following this, the Hardware description language (HDL) code is developed and tested to verify the integrity of the code. Then, the developed code is implemented on the FPGA and connected to the personal computer through Recommended Standard (RS)-232 communication to perform validation of the developed component. For the future work, the developed FPGA based encryption equipment will be verified and validated in its expected operating environment by connecting it to the Advanced power reactor (APR)-1400 simulator.

• Nuclear Engineering and Technology
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• v.55 no.8
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• pp.2873-2878
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• 2023

The purpose of this study is to perform radiation monitoring by acquiring gamma images and real-time optical images for ^99mTc vial source using charge couple device (CCD) cameras equipped with the proposed compact gamma camera. The compact gamma camera measures 86×65×78.5 mm³ and weighs 934 g. It is equipped with a metal 3D printed diverging collimator manufactured in a 45 field of view (FOV) to detect the location of the source. The circuit's system uses system-on-chip (SoC) and field-programmable-gate-array (FPGA) to establish a good connection between hardware and software. In detection modules, the photodetector (multi-pixel photon counters) is tiled at 8×8 to expand the activation area and improve sensitivity. The gadolinium aluminium gallium garnet (GAGG) measuring 0.5×0.5×3.5 mm³ was arranged in 38×38 arrays. Intrinsic and extrinsic performance tests such as energy spectrum, uniformity, and system sensitivity for other radioisotopes, and sensitivity evaluation at edges within FOV were conducted. The compact gamma camera can be mounted on unmanned equipment such as drones and robots that require miniaturization and light weight, so a wide range of applications in various fields are possible.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.2 s.314
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• pp.74-81
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• 2007

In this paper, an efficient SAD(Sum of Absolute Differences) processor structure for motion estimation of H.264 is proposed. SAD processors are commonly used both in full search methods for motion estimation and in fast search methods for motion estimation. Proposed structure consists of SAD calculator block, combinator block, and minimum value calculator block. Especially, proposed structure is simplified by using Distributed Arithmetic for addition operation. The Verilog-HDL(Hard Description Language) coding and FPGA(Field Programmable Gate Array) implementation results for the proposed structure show 39% and 32% gate count reduction in comparison with those of the conventional structure, respectively. Due to its efficient processing scheme, the proposed SAD processor structure can be widely used in size dominant H.264 chip.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2A
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• pp.147-156
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• 2004

This paper presents an implementation and performance analysis of an access channel decoder which exploits a diversity gain due to the independent magnitude of received signals energy at each of antenna elements of a smart antenna BTS (Base-station Transceiver Subsystem) operating in CDMA2000 1X signal environment. Proposed access channel decoder consists of a searcher supporting 4 fingers, Walsh demodulator, and demodulator controller. They have been implemented with 5 of 1 million-gate FPGA's (Field Programmable Gate Array) Altera's APEX EP20K1000EBC652 and TMS320C6203 DSP (digital signal processing). The objective of the proposed access channel decoders is to enhance the data retrieval at co]1-site during the access period, for which the optimal weight vector of the smart antenna BTS is not available. Through experimental tests, we confirmed that the proposed access channel decoder exploitng the diversity technique outperforms the conventional one, which is based on a single antenna channel, in terms of detection probability of access probe, access channel failure probability, and $E_{b/}$ $N_{o}$ in Walsh demodulator.r.r.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.46 no.4
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• pp.94-101
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• 2009

In this paper, we propose design of hardware based on a high speed digital signal processor (DSP) and a field programmable gate array (FPGA) for real-time suppression of fixed pattern noise (FPN) using hardware neural networks (HNN) in cooled infrared focal plane array (IRFPA) imaging system FPN appears a limited operation by temperature in observable images which applies to non-uniformity correction for infrared detector. These have very important problems because it happen serious problem for other applications as well as degradation for image quality in our system Signal processing architecture for our system operates reference gain and offset values using three tables for low, normal, and high temperatures. Proposed method creates virtual tables to separate for overlapping region in three offset tables. We also choose an optimum tenn of temperature which controls weighted values of HNN using mean values of pixels in three regions. This operates gain and offset tables for low, normal, and high temperatures from mean values of pixels and it recursively don't have to do an offset compensation in operation of our system Based on experimental results, proposed method showed improved quality of image which suppressed FPN by change of temperature distribution from an observational image in real-time system.

• Nuclear Engineering and Technology
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• v.53 no.10
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• pp.3406-3412
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• 2021

A real-time digital time-stamp sorting algorithm used in the In-Beam positron emission tomography (In-Beam PET) is presented. The algorithm is operated in the field programmable gate array (FPGA) and a small amount of registers, MUX and memory cells are used. It is developed for sorting the data of annihilation event from front-end circuits, so as to identify the coincidence events efficiently in a large amount of data. In the In-Beam PET, each annihilation event is detected by the detector array and digitized by the analog to digital converter (ADC) in Data Acquisition Unit (DAQU), with a resolution of 14 bits and sampling rate of 50 MS/s. Test and preliminary operation have been implemented, it can perform a sorting operation under the event count rate up to 1 MHz per channel, and support four channels in total, count rate up to 4 MHz. The performance of this algorithm has been verified by pulse generator and ²²Na radiation source, which can sort the events with chaotic order into chronological order completely. The application of this algorithm provides not only an efficient solution for selection of coincidence events, but also a design of electronic circuit with a small-scale structure.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.5 no.7
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• pp.1332-1339
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• 2001

SoC(System on Chip) technology is widely used in the field of embedded systems by providing high flexibility for a specific application domain. An important aspect of development any new embedded system is verification which usually requires lengthy software and hardware co-design. To reduce development cost of design effort, the instruction set of microprocessor must be suitable for a high level language compiler. And FPGA prototype system could be derived and tested for design verification. In this paper, we propose a 16 bit FPGA microprocessor, which is tentatively-named EISC16, based on an EISC(Extendable Instruction Set Computer) architecture for embedded applications. The proposed EISC16 has a 16 bit fixed length instruction set which has the short length offset and small immediate operand. A 16 bit offset and immediate operand could be extended using by an extension register and an extension flag. We developed a cross C/C++ compiler and development software of the EISC16 by porting GNU on an IBM-PC and SUN workstation and compared the object code size created after compiling a C/C. standard library, concluding that EISC16 exhibits a higher code density than existing 16 microprocessors. The proposed EISC16 requires approximately 6,000 gates when designed and synthesized with RTL level VHDL at Xilinix's Virtex XCV300 FPGA. And we design a test board which consists of EISC16 ROM, RAM, LED/LCD panel, periodic timer, input key pad and RS-232C controller. 11 works normally at 7MHz Clock.

• Journal of IKEEE
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• v.21 no.4
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• pp.388-396
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• 2017

Since there are many variables such as various poses, illuminations and occlusions in a face detection problem, a high performance detection system is required. Although CNN is excellent in image classification, CNN operatioin requires high-performance hardware resources. But low cost low power environments are essential for small and mobile systems. So in this paper, the CPU-FPGA integrated system is designed based on 3-stage cascade CNN architecture using small size FPGA. Adaptive Region of Interest (ROI) is applied to reduce the number of CNN operations using face information of the previous frame. We use a Field Programmable Gate Array(FPGA) to accelerate the CNN computations. The accelerator reads multiple featuremap at once on the FPGA and performs a Multiply-Accumulate (MAC) operation in parallel for convolution operation. The system is implemented on Altera Cyclone V FPGA in which ARM Cortex A-9 and on-chip SRAM are embedded. The system runs at 30FPS with HD resolution input images. The CPU-FPGA integrated system showed 8.5 times of the power efficiency compared to systems using CPU only.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.12
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• pp.1252-1263
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• 2009

In this paper, in order to improve a service quality and to broaden the service coverage in the mobile communication system a study on a digital RF repeater employed with an Interference Cancellation System(ICS) is performed. The digital RF repeater employed with an ICS is implemented to remove interference and feedback signals which are disadvantages of a conventional(or general) RF repeater. This thesis presents the design and experiments of the new wireless repeater. The proposed wireless repeater consists of a RF repeater mounted with digital engine. The digital ICS engine consists of a DSP and FPGA. The digital engine and RF circuit are designed into a one-piece. After developing hardware through the digital platform they are also designed and fabricated into a one-piece in order to apply a best performance repeater system. The method of removing interference and feedback signals is an adaptive IF technique employed with a LMS algorithm. The powerful performance and fast convergence speed is obtained by using this method.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.34 no.1
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• pp.110-115
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• 2006

STSAT-2 is the first satellite which will be launched by the first Korean Space Launch Vehicle(KSLV). Ground station Baseband Control system(GBC) is now developed for STSAT-2. GBC has two functions. One is control data path between satellite control computers and ground station antennas(1.5M, 3.7M, 13M) automatically. The other is sending and receiving data between ground station and satellite. GBC is implemented by FPGA(Field-Programmable Gate Array) which includes almost all logic(for MODEM, PROTOCOL and GBC system control). MODEM in GBC has two uplink FSK modulators(1.2[kbps], 9.6[kbps]) and six downlink FSK demodulators(9.6[kbps], 38.4[kbps]). In hardware, STSAT-2 GBC is smaller than STSAT-1 GBC. In function, STSAT-2 GBC has more features than STSAT-1 GBC. This paper is about GBC structure, functions and test results.