• Journal of Institute of Control, Robotics and Systems
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• 제10권1호
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• pp.73-80
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• 2004

We have developed a general purpose motion controller using an FPGA(Field Programmable Gate Array). The multi-PID controllers and GUI are implemented as a system-on-chip for multi-axis motion control. Comparing with the commercial motion controller LM 629, since it has multi-independent PID controllers, we have several advantages such as space effectiveness, low cost and lower power consumption. In order to test the performance of the proposed controller, motion of the robot hand is controlled. The robot hand has three fingers with 2 joints each. Finger movements show that tracking was very effective. Another experiment of balancing an inverted pendulum on a cart has been conducted to show the generality of the proposed FPGA PID controller. The controller has well maintained the balance of the pendulum.

• Journal of Practical Engineering Education
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• 제6권2호
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• pp.91-97
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• 2014

Education equipment for field programmable gate array (FPGA) based multimedia player design is introduced. Using the education equipment, an example of hardware design for color detection and augment reality (AR) game is described, and an example of syllabus for "Digital system design using FPGA" course is introduced. Using the education equipment, students can develop the ability to design some hardware, and to train the ability for the creative capstone design through conceptual, partial-level, and detail designs. By controlling audio codec, system-on-chip (SOC) design skills combining a NIOS II soft microprocessor and digital hardware in one FPGA chip are improved. The ability to apply wireless communication and LabView to FPGA-based digital design is also increased.

• Nuclear Engineering and Technology
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• 제48권4호
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• pp.1047-1057
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• 2016

Design engineering process for field programmable gate array (FPGA)-based reactor trip functions are developed in this work. The process discussed in this work is based on the systems engineering approach. The overall design process is effectively implemented by combining with design and implementation processes. It transforms its overall development process from traditional V-model to Y-model. This approach gives the benefit of concurrent engineering of design work with software implementation. As a result, it reduces development time and effort. The design engineering process consisted of five activities, which are performed and discussed: needs/systems analysis; requirement analysis; functional analysis; design synthesis; and design verification and validation. Those activities are used to develop FPGA-based reactor bistable trip functions that trigger reactor trip when the process input value exceeds the setpoint. To implement design synthesis effectively, a model-based design technique is implied. The finite-state machine with data path structural modeling technique together with very high speed integrated circuit hardware description language and the Aldec Active-HDL tool are used to design, model, and verify the reactor bistable trip functions for nuclear power plants.

• The Transactions of the Korean Institute of Power Electronics
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• 제12권4호
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• pp.339-345
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• 2007

This paper presents a design of an FPGA (Field Programmable Gate Array) -based currentcontroller. Using the nature of the high computational capability of FPGA, the digital delay due to the algorithm execution can be reduced. The control performance can be better than the conventional DSP (Digital Signal Processor)-based current controller. Moreover, this method does not need any delay compensation algorithm because the digital delay is physically diminished. Therefore, the bandwidth of the current controller can be extended by this method. The feasibility of this method is verified by several experimental results under the various conditions.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.360-365
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• 2003

In this paper, we have developed a general purpose motion controller using an FPGA(Field Programmable Gate Array). The multi-PID controllers on a single chip are implemented as a system-on-chip for multi-axis motion control. We also develop a PC GUI for an efficient interface control. Comparing with the commercial motion controller LM 629 it has multi-independent PID controllers so that it has several advantages such as space effectiveness, low cost and lower power consumption. In order to test the performance of the proposed controller, robot finger is controlled. The robot finger has three fingers with 2 joints each. Finger movements show that position tracking was very effective. Another experiment of balancing an inverted pendulum on a cart has been conducted to show the generality of the proposed FPGA PID controller. The controller has well maintained the balance of the pendulum.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• 제21권4호
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• pp.43-49
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• 2021

A small infrared image homing system is a tracking system that has an infrared image sensor that identifies a target through the day and night infrared image processing of the target on the ground and searches for and detects the target with respect to the main target. This paper describes the development of a board equipped with a high-speed CPU and FPGA (Field Programmable Gate Array) to identify target through real-time image processing by acquiring target information through infrared image. We propose a CPU-FPGA combining architecture for CPU and FPGA selection and video signal processing, and also describe a controller design using FPGA to control infrared sensor.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• 한국항해항만학회 2022년도 추계학술대회
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• pp.388-389
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• 2022

Recently, AI (Artificial Intelligence) has been applied to various technologies such as automatic driving, robot and smart communication. Currently, AI system is developed by software-based method using tensor flow, and GPU (Graphic Processing Unit) is employed for processing unit. However, if software-based method employing GPU is used for AI applications, there is a problem that we can not change the internal circuit of processing unit. In this method, if high-level jobs are required for AI system, we need high-performance GPU, therefore, we have to change GPU or graphic card to perform the jobs. In this work, we developed a CNN-based FPGA (Field Programmable Gate Array) chip to solve this problem.

• Journal of KIISE
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• 제43권5호
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• pp.569-578
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• 2016

The PLC (Programmable Logic Controller) has been widely used for the development of digital control system of nuclear power plant. The PLC has high maintenance costs and increasing complexity, hence, FPGA (Field Programmable Gate Array) based digital control system has been considered as an alternative. However, the development of FPGA based digital control system is a challenge for PLC engineers because they are required to learn about new language to develop FPGA and knowledge and know-how acquired in the development of PLC is not transferable. In this study, we proposed and implemented an automatic translation tool for translation of FBD (Function Block Diagram), a programming language of PLC software, into VHDL (VHSIC Hardware Description Language). Automatically translating the FBD to VHDL using this tool allows PLC engineers to develop FPGA without any knowledge of the hardware description language.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 한국정밀공학회 2007년도 춘계학술대회 논문집
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• pp.59-60
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• 2007

• Journal of the Korea Society of Computer and Information
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• 제7권4호
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• pp.115-120
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• 2002

This paper presents the implementation of IS-95 CDMA signal processor, baseband and Intermediate Frequency(IF) digital converter using Field Programmable Gate Array(FPGA) and ADC/DAC and frequency up/down converter IS-95 CDMA channel processor is generated the pilot channel signal with short PN code and Walsh-code generator. The digital If is composed of FPGA. digital transmit/receive signal processor and high speed analog-to-digital converter(ADC) and digital-to-analog converter(DAC). The frequency up/down converter consisted of filter, mixer, digital attenuator and PLL is analog conversion between intermediate frequency(IF) and baseband. This implemented system can be deployed in the IS-95 CDMA base station device etc.