• The Transactions of The Korean Institute of Electrical Engineers
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• v.59 no.3
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• pp.664-668
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• 2010

This paper presents a System-On-a-chip (SoC) for embedded image processing and pattern recognition applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• 제어로봇시스템학회:학술대회논문집
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• 2002.10a
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• pp.84.5-84
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• 2002

In order to be a stand-alone structure, a biped robot should be designed of the effective mechanic structure and the smaller hardware system. This paper shows the design methodology of a biped robot controller using FPGA(Field Programmable Gate Array). A hardware system consists of DSP(Digital Signal Processor) as the main CPU and FPGA as the motor controller...

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1346-1349
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• 2002

This paper presents the design and implementation of 16-QAM modem that can be applied to fixed broadband wireless access systenm. It is implemented in the hardware prototype that consist of FPGA(Field Programmable Gate Array) for digital signal processing and analog front end module for analog signal processing. We provide 20.48Mbps data rate using implemented modem and test the modem in KOREA 26㎓ broadband wireless local loop system including IFU(Intermediate Frequency Unit) and RFU(Radio Frequency Unit) via air interface.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2001.11a
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• pp.403-406
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• 2001

본 논문에서는 차세대 표준 알고리즘(AES: Advanced Encryption Standard)인 Rijndael 알고리즘의 고속화를 FPGA로 구현하였다. Rijndael 알고리즘은 미국 상무부 기술 표준국(NIST)에 의해 2000년 10월에 차세대 표준으로 선정된 블록 암호 알고리즘이다. FPGA(Field Programmable Gate Array)는 아키텍쳐의 유연성이 가장 큰 장점이며, 근래에는 성능면에서도 ASIC에 비견될 정도로 향상되었다. 본 논문에서는 128비트 키 길이와 블록 길이를 가지는 암호화(Encryption)블럭을 Xilinx VirtexE XCV812E-8-BG560 FPGA에 구현하였으며 약 15Gbits/sec의 성능(throughput)을 가진다. 이는 현재까지 발표된 FPGA Rijndael 알고리즘의 구현 사례 중 가장 빠른 방법 중의 하나이다.

• Journal of Korea Multimedia Society
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• v.19 no.7
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• pp.1154-1158
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• 2016

This paper presents a System-On-a-chip for embedded image processing applications that need Gaussian Pyramid structure. The system is fully implemented into Field-Programmable Gate Array (FPGA) based on the prototyping platform. The SoC consists of embedded processor core and a hardware accelerator for Gaussian Pyramid construction. The performance of the implementation is benchmarked against software implementations on different platforms.

• Journal of Sensor Science and Technology
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• v.7 no.5
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• pp.364-371
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• 1998

A novel antifuse has been developed for field programmable gate arrays (FPGA's) as a voltage programmable link with Al/$BaTiO_3/SiO_2$/TiW-silicide. The proper program voltage can be obtained by adjusting the deposition thickness of $BaTiO_3$ film. When a negative voltage was applied at bottom TiW-silicide electrode of the antifuse, based on $BaTiO_3(120{\AA})$/$SiO_2(120{\AA})$, the program voltage was about l4.4V and on-resistances were ranged between 40 and $50{\Omega}$. The current-voltage characteristics of antifuses are consistent with a Frenkel-Poole conduction model. However, there are some deviations depending on bias polarity that are probably due to the difference in the interface properties between Al/$BaTiO_3$ and TiW-silicide/$SiO_2$.

• Journal of the Korean Vacuum Society
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• v.17 no.4
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• pp.253-261
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• 2008

Programmable metallizaton cell (PMC) memory device has been known as one of the next generation non-volatile memory devices, because it includes non-volatility, high speed and high ON/OFF resistance ratio. This paper reviews the operation principle of the device. Besides, the recent research results of professor Kozicki who firstly invented the device and investigated it for the memory applications, NEC corporation which studied it for the FPGA (field programmable gate array) switch applications, ETRI and chungnam national university which examined Te-based devices are introduced.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.2
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• pp.125-134
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• 1994

This paper proposes a new top-down technology mapping algorithm for minimizing the chip area and the path delay time of lookup table-based field programmable gate array(FPGA). First, we present the decomposition and factoring algorithm using common subexpre ssion which minimizes the number of basic logic blocks and levels instead of the number of literals. Secondly, we propose a cube packing algorithm considering the decomposition of gates which exceed m-input lookup table. Previous approaches perform the cube packing and the gate decomposition independently, and it causes to increase the number of basic logic blocks. Lastly, the efficiency.

• Journal of Korea Society of Digital Industry and Information Management
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• v.9 no.1
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• pp.95-102
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• 2013

This paper covers nulling algorithm. In this algorithm, we assume that nulling points are already known. In general, nulling algorithm using matrix equation was utilized. But, this algorithm is pointed out that computational complexity is disadvantage. So, we choose gradient method to reduce the computational complexity. In order to further reduce the computational complexity, we propose approximate gradient method using characteristic of trigonometric functions. The proposed method has same performance compared with conventional method while having half the amount of computation when the number of antenna and nulling point are 20 and 1, respectively. In addition, we could virtually eliminate the trigonometric functions arithmetic. Trigonometric functions arithmetic cause a big problem in actual implementation like FPGA processor(Field Programmable gate array). By utilizing the above algorithm in a multi-cell environment, beamforming gain can be obtained and interference can be reduced at same time. By the above results, the algorithm can show excellent performance in the cell boundary.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.11
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• pp.5465-5470
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• 2012

FPGA(Field Programmable Gate Array) devices are widely used due to their merits in circuit development time, and development cost. Among various FPGA technologies, SRAM-based FPGAs have large cell capacity so that they are attractive for complex circuit design and their reconfigurability. However, they are weak in space environment where radiation energy particles cause Single Event Upset(SEU). In this paper, we designed a controller supervising SRAM-based FPGA to protect configuration memory inside. The controller is implemented on an Anti-Fusing FPGA. Radiation test was performed on the implemented computer board and the result show that our controller provides better SEU-resilience than TMR-only system.