• Title/Summary/Keyword: Field Effect Transistor (FET)

Search Result 237, Processing Time 0.028 seconds

Dielectric Layer Planarization Process for Silicon Trench Structure (실리콘 트랜치 구조 형성용 유전체 평탄화 공정)

  • Cho, Il Hwan;Seo, Dongsun
    • Journal of IKEEE
    • /
    • v.19 no.1
    • /
    • pp.41-44
    • /
    • 2015
  • Silicon trench process for bulk fin field effect transistor (finFET) is suggested without using chemical mechanical polishing (CMP) that cause contamination problems with chemical stuff. This process uses thickness difference of photo resistor spin coating and silicon nitride sacrificial layer. Planarization of silicon oxide and silicon trench formation can be performed with etching processes. In this work 50 nm silicon trench is fabricated with AZ 1512 photo resistor and process results are introduced.

Reduced Graphene Oxide Field-Effect Transistor for Temperature and Infrared Sensing

  • Trung, Tran Quang;Tien, Nguyen Thanh;Kim, Do-Il;Lee, Nae-Eung
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2012.02a
    • /
    • pp.552-552
    • /
    • 2012
  • We fabricated reduced graphene oxide field-effect transistor (RGO-FET) on glass for highly sensitive temperature and IR detection. The device has the channels of RGO responsive to physical stimuli such as temperature and IR. The RGO sensing layers are fabricated from exfoliated graphene oxide sheets that are deposited to form a thin continuous network by electrostatic assembly. These graphene oxide networks are reduced toward reduce graphene oxide by exposure to a hydrazine hydrate vapor. To improve performance and eliminate interferences from oxygen and water vapor absorption to electrical properties of RGO-FET, the sensor devices were encapsulated by the tetratetracontane layer after annealing treatment. The device with encapsulation layer showed lower hysteresis, improved stability, and better repeatability. The temperature response of RGO-FET is examined by measuring changing the temperature, the device exhibited the high sensitivity and repeatability even with the temperature interval of 1 K. We also demonstrated that our devices have capability of IR sensing.

  • PDF

Electrical properties and contact energy barrier of ZnO nanowire field effect transistor (ZnO 나노선 FET에서의 접촉 에너지 장벽의 전기적 특성 연구)

  • Kim, Kang-Hyun;Yim, Chan-Young;Kim, Hye-Young;Kim, Gue-Tak;Kang, Hae-Yong;Lee, Jong-Su;Kang, Woun
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2005.07a
    • /
    • pp.13-14
    • /
    • 2005
  • ZnO 단일 나노선 field effect transistor (FET) 소자의 2단자 전류-전압 특성을 조사해 보면 n-type 반도체 특성이 나타남을 알 수 있다. 그러나 2단자로 측정 할 경우 반도체 나노선과 금속 전극사이에 존재하는 접촉저항의 영향이 필연적으로 포함된다. 따라서 측정한 결과가 나노선에 의해서 나타나는 고유한 특성인지 접촉저항의 원인이 되는 에너지 장벽의 성질인지 명확히 밝힐 필요가 있다. 그래서 이번 연구에서는 4단자 측정방법을 이용하여 접촉저항 성분을 배제한 소자의 고유한 성질을 밝혀낼 뿐만 아니라, 이것을 2단자의 결과와 비교함으로써 접촉점에서 나타나는 에너지 장벽의 특징도 파악해 낼 수 있었다. 실험에서 사용된 ZnO FET 소자의 경우, 접촉점에서 생기는 에너지 장벽을 터널링을 통해 극복하는 것으로 분석되었고 이는 온도 변화에 따른 4 단자 및 2 단자 전류-전압 측정을 통해 확인될 수 있었다.

  • PDF

Device characterization and Fabrication Issues for Ferroelectric Gate Field Effect Transistor Device

  • Yu, Byoung-Gon;You, In-Kyu;Lee, Won-Jae;Ryu, Sang-Ouk;Kim, Kwi-Dong;Yoon, Sung-Min;Cho, Seong-Mok;Lee, Nam-Yeal;Shin, Woong-Chul
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.2 no.3
    • /
    • pp.213-225
    • /
    • 2002
  • Metal-Ferroelectric- Insulator- Silicon (MFIS) structured field effect transistor (FET) device was fabricated and characterized. Important issues to realize ferroelectric gate field effect transistor device were summarized in three sections. The choice of interlayer dielectric was made in the consideration of device functionality and chemical reaction between ferroelectric materials and silicon surface during fabrication process. Also, various ferroelectric thin film materials were taken into account to meet desired memory window and process compatibility. Finally, MFIS structured FET device was fabricated and important characteristics were discussed. For feasible integration of current device as random access memory array cell address schemes were also suggested.

Sense Amplifier Design for A NOR Type Non-Volatile Memory

  • Yang, Yil-Suk;Yu, Byoung-Gon;Roh, Tae-Moon;Koo, Jin-Gun;Kim, Jongdae
    • Proceedings of the IEEK Conference
    • /
    • 2002.07c
    • /
    • pp.1555-1557
    • /
    • 2002
  • We have investigated the precharge type sense amplifier, it is suitable fur voltage sensing in a NOR type single transistor ferroelectric field effect transistor (1T FeFET) memory read operation. The proposed precharge type sense amplifier senses the bit line voltage of 1T FeFET memory. Therefore, the reference celt is not necessary compared to current sensing in 1T FeFET memory, The high noise margin is wider than the low noise margin in the first inverter because requires tile output of precharge type sense amplifier high sensitivity to transition of input signal. The precharge type sense amplifier has very simple structure and can sense the bit line signal of the 1T FeFET memory cell at low voltage.

  • PDF

Design of Parasitic Inductance Reduction in GaN Cascode FET for High-Efficiency Operation

  • Chang, Woojin;Park, Young-Rak;Mun, Jae Kyoung;Ko, Sang Choon
    • ETRI Journal
    • /
    • v.38 no.1
    • /
    • pp.133-140
    • /
    • 2016
  • This paper presents a method of parasitic inductance reduction for high-speed switching and high-efficiency operation of a cascode structure with a low-voltage enhancement-mode silicon (Si) metal-oxide-semiconductor field-effect transistor (MOSFET) and a high-voltage depletion-mode gallium nitride (GaN) fielde-ffect transistor (FET). The method is proposed to add a bonding wire interconnected between the source electrode of the Si MOSFET and the gate electrode of the GaN FET in a conventional cascode structure package to reduce the most critical inductance, which provides the major switching loss for a high switching speed and high efficiency. From the measured results of the proposed and conventional GaN cascode FETs, the rising and falling times of the proposed GaN cascode FET were up to 3.4% and 8.0% faster than those of the conventional GaN cascode FET, respectively, under measurement conditions of 30 V and 5 A. During the rising and falling times, the energy losses of the proposed GaN cascode FET were up to 0.3% and 6.7% lower than those of the conventional GaN cascode FET, respectively.

Electrical Properties of Field Effect Transistor using F16CuPc (F16CuPc를 이용한 Field Effect Transistor의 전기적 특성 연구)

  • Lee, Ho-Shik;Park, Young-Pil;Cheon, Min-Woo
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
    • /
    • 2008.11a
    • /
    • pp.389-390
    • /
    • 2008
  • We fabricated organic field-effect transistors (OFETs) based a fluorinated copper phthalocyanine ($F_{16}CuPc$) as an active layer. And we observed the surface morphology of the $F_{16}CuPc$ thin film. The $F_{16}CuPc$ thin film thickness was 40nm, and the channel length was $50{\mu}m$, channel width was 3mm. We observed the typical current-voltage (I-V) characteristics and capacitance-voltage (C-V) in $F_{16}CuPc$ FET and we calculated the effective mobility.

  • PDF

Label-free Femtomolar Detection of Cancer Biomarker by Reduced Graphene Oxide Field-effect Transistor

  • Kim, Duck-Jin;Sohn, Il-Yung;Jung, Jin-Heak;Yoon, Ok-Ja;Lee, N.E.;Park, Joon-Shik
    • Proceedings of the Korean Vacuum Society Conference
    • /
    • 2012.02a
    • /
    • pp.549-549
    • /
    • 2012
  • Early detection of cancer biomarkers in the blood is of vital importance for reducing the mortality and morbidity in a number of cancers. From this point of view, immunosensors based on nanowire (NW) and carbon nanotube (CNT) field-effect transistors (FETs) that allow the ultra-sensitive, highly specific, and label-free electrical detection of biomarkers received much attention. Nevertheless 1D nano-FET biosensors showed high performance, several challenges remain to be resolved for the uncomplicated, reproducible, low-cost and high-throughput nanofabrication. Recently, two-dimensional (2D) graphene and reduced GO (RGO) nanosheets or films find widespread applications such as clean energy storage and conversion devices, optical detector, field-effect transistors, electromechanical resonators, and chemical & biological sensors. In particular, the graphene- and RGO-FETs devices are very promising for sensing applications because of advantages including large detection area, low noise level in solution, ease of fabrication, and the high sensitivity to ions and biomolecules comparable to 1D nano-FETs. Even though a limited number of biosensor applications including chemical vapor deposition (CVD) grown graphene film for DNA detection, single-layer graphene for protein detection and single-layer graphene or solution-processed RGO film for cell monitoring have been reported, development of facile fabrication methods and full understanding of sensing mechanism are still lacking. Furthermore, there have been no reports on demonstration of ultrasensitive electrical detection of a cancer biomarker using the graphene- or RGO-FET. Here we describe scalable and facile fabrication of reduced graphene oxide FET (RGO-FET) with the capability of label-free, ultrasensitive electrical detection of a cancer biomarker, prostate specific antigen/${\alpha}$ 1-antichymotrypsin (PSA-ACT) complex, in which the ultrathin RGO channel was formed by a uniform self-assembly of two-dimensional RGO nanosheets, and also we will discuss about the immunosensing mechanism.

  • PDF

An analytical consideration of the MOS type field-effect transistor differential amplifier (MOS형 전계효과 트랜지스터 차동증폭기에 관한 소고)

  • 정만영
    • 전기의세계
    • /
    • v.14 no.6
    • /
    • pp.1-7
    • /
    • 1965
  • This paper provides the analysis of the differential amplifier using the insulated gate, metala-oxide-semiconductor type field-effect-transistor(MOS FET), for its active element and the power drift of the amplifer. From these analytical considerations some design standardsn were found for the MOS FET differential amplifier available for the measurement of the very small current (pico-ampare range). A differential amplifier was designed and built in the view of above considerations. Its equivalent input gate voltages of the thermal drift and the power drift were 0.57mV/.deg. C in the range 25.deg. C-60.deg. C and 8.8mV/V in the range of 20% drift of its orginal value, respectively.

  • PDF

Recent Development in Polymer Ferroelectric Field Effect Transistor Memory

  • Park, Youn-Jung;Jeong, Hee-June;Chang, Ji-Youn;Kang, Seok-Ju;Park, Cheol-Min
    • JSTS:Journal of Semiconductor Technology and Science
    • /
    • v.8 no.1
    • /
    • pp.51-65
    • /
    • 2008
  • The article presents the recent research development in polymer ferroelectric non-volatile memory. A brief overview is given of the history of ferroelectric memory and device architectures based on inorganic ferroelectric materials. Particular emphasis is made on device elements such as metal/ferroelectric/metal type capacitor, metal-ferroelectric-insulator-semiconductor (MFIS) and ferroelectric field effect transistor (FeFET) with ferroelectric poly(vinylidene fluoride) (PVDF) and its copolymers with trifluoroethylene (TrFE). In addition, various material and process issues for realization of polymer ferroelectric non-volatile memory are discussed, including the control of crystal polymorphs, film thickness, crystallization and crystal orientation and the unconventional patterning techniques.