• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.2
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• pp.64-70
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• 2009

A 6-Gbps feed-forward equalizer having a 6.2-dB gain at 3GHz is designed in 0.13-um CMOS technology and the equalizer helps error-free data recovery over a 7-m SATA cable with 14.7dB loss. Based on a differentially-connected varactor, the proposed equalizer uses only a one-fourth varactor size of a conventional equalizer, which enables the equalizer's integration in a pad-frame, high operating frequency, and low power dissipation of 3.6mW.

• Journal of information and communication convergence engineering
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• v.14 no.2
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• pp.78-83
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• 2016

In underwater acoustic communication, the transmitted signals are severely influenced by the reflections from both the sea surface and the sea bottom. As very large reflection signals from these boundaries cause an inter-symbol interference (ISI) effect, the communication quality worsens. A channel estimation-based equalizer is usually adopted to compensate for the reflected signals under the acoustic communication channel. In this study, a feed-forward equalizer (FFE) with the least mean squares (LMS) algorithm was applied to a quadrature phase-shift keying (QPSK) transmission system. Two different types of equalizers were adopted in the QPSK system, namely a real-coefficient equalizer and a complex-coefficient equalizer. The performance of the complex-coefficient equalizer was better than that of two real-coefficient equalizers. Therefore, a Hilbert transform was applied to the real-coefficient binary phase-shift keying (BPSK) system to obtain a complex-coefficient BPSK system. Consequently, we obtained better results than those of a real-coefficient equalizer.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.5
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• pp.50-57
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• 2007

A 5Gbps CMOS　adaptive feed-forward equalizer designed for backplane applications is described. The equalizer has adaptive feedback circuits to control the compensating gain of the equalizing filter, which uses a phase detector in clock recovery circuit to detect ISI (Inter-Symbol Interference) level. This makes the equalizer operate adaptively for a various channel length of backplane environments.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.12A
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• pp.933-940
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• 2009

This paper proposes a robust detection scheme for quasi-orthogonal space-time block code over time-selective fading channels. The proposed detector performs interference cancellation and decision feedback equalization to remove the inter-antenna interference and inter-symbol interference when the channel varies from symbol to symbol. Cholesky factorization is used on the channel Gram matrix after performing interference cancellation to obtain feed forward equalizer and feedback equalizer. It is shown by simulations that the proposed detection scheme outperforms the conventional detection schemes and the exiting detection schemes to time-selectivity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.2
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• pp.253-260
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• 2018

The acoustic communication channel in shallow underwater is typically shown as time-varying multipath fading channel characteristics. The received signal through channel transmission cause inter-symbol interference (ISI) owing to multiple components of different time delay and amplitude. To compensate for this, several techniques have been used, and one of them is acoustic equalizer. In this study, we used four equalizers - feed forward equalizer (FFE), decision directed equalizer (DDE), decision feedback equalizer (DFE) and combination DDE with DFE to compensate ISI. And we applied two adaptive algorithms to adjust coefficient of equalizers - normalized least mean square algorithm and recursive least square algorithm. As result, we found that it has a significant performance improvement over 6 dB on SNR in nonlinear equalizer. By combination of DFE and DDE has almost best performance in any case.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.8
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• pp.1765-1772
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• 2015

In the underwater acoustic communication channels, multipath reflection become the cause of obstacle. Generally, equalizer has been applied to overcome these problems. In this paper, the method was proposed to optimize tap-length of decision feedback equalizer using genetic algorithm. After inputting feed-forward filter length and feed-back filter length as genetic information of the genetic algorithm, it optimize tap-length using BER(bit error rate) calculation in accordance with object function. The object function consist of decision feedback equalizer and BER calculation. For the purpose of BER calculation in the object function, the method was proposed to optimize the tap-length of decision feedback equalizer with genetic algorithm using preamble signals. As a result of experiments, the optimized BER is 0.0355 for signals which were received through a 25m receiver and which were applied to calculate BER merely using preamble signals in object function. When all data were used to calculate BER in object function, the optimized BER is 0.0215.

• The Journal of the Acoustical Society of Korea
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• v.29 no.5
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• pp.303-313
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• 2010

This paper describes an acoustic communication receiver structure, which is designed for QPSK (Quadrature Phase Shift Keying) signal with 25 kHz carrier frequency and 5 kHz symbol rate, and takes samples from received signal at 100 kHz sampling rate. Based on the described receiver structure, optimum design parameters, such as number of taps of FF (Feed-Forward) and FB (Feed-Back) filters and forgetting factor of RLS (Recursive Least-Square) algorithm, of joint equalizer are determined to minimize the BER (Bit Error Rate) performance of the joint equalizer output symbols when the acquisition data in shallow water using implemented acoustic transducers is decimated at a rate of 2:1 and then enforced to the input of receiver. The transmission distances are 1.4 km, 2.9 km, and 4.7 km. Analysis results show that the optimum number of taps of FF and FB filters are different according to the distance between source and destination, but the optimum or near optimum value of forgetting factor is 0.997. Therefore, we can reach a conclusion that the proper receiver structure could change the number of taps of FF and FB filters with the fixed forgetting factor 0.997 according to the transmission distance. Another analysis result is that there are an acceptable performance degradation when the 16-tap-length simple filter is used as a low-pass filter of receiver instead of 161-tap-length matched filter.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.39 no.6
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• pp.709-717
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• 2002

A new multi constant modulus algorithm (MCMA) for a blind decision feedback equalizer is proposed. In order to avoid the error propagation problem in the conventional DFE structure, Feed-Back Filter coefficients are updated only after Feed-Forward Filter coefficients are sufficiently converged to the steady state. Therefore, it has the problem of slow convergence speed characteristics. To overcome this drawback, the proposed MCMA algorithm uses not only new cost function considering the minimum distance between the received signal and the representative value containing the statistical characteristics of the transmitted signal, but also adaptive step-size according to the equalizer outputs to fast convergence speed of FBF. Simulations were carried out under the certified communication channel environment to evaluate a performance of the proposed equalizer. The simulation results show that the proposed equalizer has an improved convergence and SER performance compared with previous methods. The proposed techniques offer the possibility of practical equalization for cable modem and terrestrial HDTV broadcast (using 8-VSB or 64-QAM) applications.

• Journal of IKEEE
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• v.14 no.1
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• pp.33-39
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• 2010

In this paper, a 5Gb/s receiver with an adaptive equalizer for serial link interfaces is proposed. For effective gain control, a least-mean-square (LMS) algorithm was implemented with two internal signals of slicers instead of output node of an equalizing filter. The scheme does not affect on a bandwidth of the equalizing filter. It also can be implemented without passive filter and it saves chip area and power consumption since two internal signals of slicers have a similar DC magnitude. The proposed adaptive equalizer can compensate up to 25dB and operate in various environments, which are 15m shield-twisted pair (STP) cable for DisplayPort and FR-4 traces for backplane. This work is implemented in $0.18-{\mu}m$ 1-poly 4-metal CMOS technology and occupies $200{\times}300{\mu}m^2$. Measurement results show only 6mW small power consumption and 2Gbps operating range with fabricated chip. The equalizer is expected to satisfy up to 5Gbps operating range if stable varactor(RF) is supported by foundry process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.12A
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• pp.2015-2024
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• 1999

Presented in this paper are a new complex-umber filter architecture, which is suitable for an efficient implementation of baseband signal processing of digital communication systems, and a chip-set design of adaptive decision-feedback equalizer (ADFE) employing the proposed structure. The basic concept behind the approach proposed in this paper is to apply redundant binary (RB) arithmetic instead of conventional 2’s complement arithmetic in order to achieve an efficient realization of complex-number multiplication and accumulation. With the proposed way, an N-tap complex-number filter can be realized using 2N RB multipliers and 2N-2 RB adders, and each filter tap has its critical delay of $T_{m.RB}+T_{a.RB}$ (where $T_{m.RB}, T_{a.RB}$are delays of a RB multiplier and a RB adder, respectively), making the filter structure simple, as well as resulting in enhanced speed by means of reduced arithmetic operations. To demonstrate the proposed idea, a prototype ADFE chip-set, FFEM (Feed-Forward Equalizer Module) and DFEM (Decision-Feedback Equalizer Module) that can be cascaded to implement longer filter taps, has been designed. Each module is composed of two complex-number filter taps with their LMS coefficient update circuits, and contains about 26,000 gates. The chip-set was modeled and verified using COSSAP and VHDL, and synthesized using 0.8- μm SOG (Sea-Of-Gate) cell library.