• International journal of advanced smart convergence
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• v.7 no.3
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• pp.92-100
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• 2018

In this paper, we propose a fault-tolerant scheduling scheme with energy efficiency for real-time periodic tasks on DVFS-enabled multicore processors. The scheme provides the tolerance of a permanent fault with the primary-backup task model. Also the scheme reduces the energy consumption of real-time tasks with the fully overlapped execution between each primary task and its backup task, whereas most of previous methods tried to minimize the overlapped execution between the two tasks. In order to the leakage energy loss of idle cores, the scheme activates a part of available cores with rarely used cores powered off. Evaluation results show that the proposed scheme saves up to 82% energy consumption of the previous method.

• Journal of the Korea Society of Computer and Information
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• v.10 no.4 s.36
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• pp.149-154
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• 2005

Computer center of university or company manages many non fault-tolerant servers and network devices to spare expenses. Because a service fault occurs sometimes by worm virus, system bug etc, we need a technique to detect it for continuing service. This paper introduces design and implementation of the system to observe many heterogeneous services, and web-based interface improving convenience of system manager. A system fault is reported to system managers via email or SMS by introduced service observation system, not service user. Then system managers can recover the system fault by this notification and minimize a fault period.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.2
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• pp.307-311
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• 2015

In this paper, we propose an efficient fault-recovery technique for CGRA (Coarse-Grained Reconfigurable Architecture) based multi-core architecture. The proposed technique is intra/inter-CGRA co-reconfiguration technique based on a ring-based sharing fabric (RSF) and it enables exploiting the inherent redundancy and reconfigurability of the multi-CGRA for fault-recovery. Experimental results show that the proposed approaches achieve up to 73% fault recoverability when compared with completely connected fabric (CCF).

• Journal of Advanced Navigation Technology
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• v.14 no.2
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• pp.233-238
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• 2010

In this paper, we applied the forward and backward error recovery techniques to a reduced instruction set computer (risc) processor to develop two fault-tolerant processors, namely, fetch redundant risc (FRR) processor and a redundancy execute risc (RER) processor. To evaluate the fault-tolerance capability of three target processors, we developed the base risc processor, FRR processor, and RER processor in SystemC hardware description language. We performed fault injection experiment using the three SystemC processor models and the SystemC-based simulation fault injection technique. From the experiments, for the 1-bit transient fault, the failure rate of the FRR, RER, and base risc processor were 1%, 2.8%, and 8.9%, respectively. For the 1-bit permanent fault, the failure rate of the FRR, RER, and base risc processor were 4.3%, 6.5%, and 41%, respectively. As a result, for 1-bit fault, we found that the FRR processor is more reliable among three processors.

• Journal of Institute of Control, Robotics and Systems
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• v.19 no.9
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• pp.822-826
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• 2013

In this paper, we propose an AFDO (Adaptive Fault Diagnosis Observer) and a fault tolerant controller for a class of nonlinear continuous-time system under the nonlinear abrupt actuator faults. Together with its estimation laws, the AFDO which estimates that the actuator faults is designed by using the Lyapunov analysis. Then, based on the designed AFDO, an adaptive sliding mode controller is proposed as the fault tolerant controller. Using Lyapunov stability analysis, we also prove the uniform boundedness of the state, the output and the fault estimation errors, and the asymptotic stability of the tracking error under the nonlinear time-varying faults. Finally, we illustrate the effectiveness of the proposed diagnosis method and the control scheme thorough computer simulations.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.18 no.10
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• pp.1553-1571
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• 1993

A significant amount of research has focused on the development of highly parallel architectures to obtain far more computational power than conventional computer systems. These architectures usually comprise of a large number of processors communicating through an interconnection network. The VLSI (Very Large Scale Integration) and WSI (Wafer Scale Integration) cellular arrays form one important class of those parallel architectures, and consist of a large number of simple processing cells, all on a single chip or wafer, each interconnected only to its neighbors. This paper studies three fundamental issues in these arrays : fault-tolerant reconfiguration. functional reconfiguration, and their integration. The paper examines conventional techniques, and gives an in-depth discussion about fault-tolerant reconfiguration and functional reconfiguration, presenting testing control strategy, configuration control strategy, steps required f4r each reconfiguration, and other relevant topics. The issue of integrating fault tolerant reconfiguration and functional reconfiguration has been addressed only recently. To tackle that problem, the paper identifies the relation between fault tolerant reconfiguration and functional reconfiguration, and discusses appropriate testing and configuration control strategy for integrated reconfiguration on VLSI and WSI cellular arrays.

• KIPS Transactions on Computer and Communication Systems
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• v.3 no.12
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• pp.443-448
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• 2014

This paper is a study related to fault tolerant design based on PSTR using virtualization techniques. If the fault tolerant PSTR based on virtualization techniques is implemented the communication performance between primary and shadow will improves and monitoring function is easy to available about activities of primary and shadow. The legacy PSTR model is implemented in its hardware. The primary play a main role and shadow play a switched action when the errors occurrs in the primary. The switched action of shadow make it possible to restart the primary function newly. This paper implements fault tolerant primary-shadow model using virtualization techniques on the embedded environment.

• International Journal of Automotive Technology
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• v.7 no.2
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• pp.201-208
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• 2006

This paper describes the control philosophy of ESP(Electronic Stability Program) which consists of the stability control the fault diagnosis and the fault tolerant control. Besides the functional performance of the stability control, robustness of control and fault diagnosis is focused to avoid the unnecessary activation of the controller. The look-up tables are mentioned to have the accurate target yaw rate of the vehicle and obtained from vehicle tests for the whole operation range of the steering wheel angle and the vehicle speed. The wheel slip control with a design goal of wheel slip invariance is implemented for the yaw compensation and the target wheel slip is determined by difference between the target yaw rate and actual yaw rate. Since the ESP has a high severity level and the robust control is required, the robustness margin for the stability control is determined according to several uncertainties and the robust fault diagnosis is performed. Both computer simulation and test results are shown in this paper.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.318-328
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• 2011

Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

• Journal of Sensor Science and Technology
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• v.16 no.1
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• pp.52-61
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• 2007

Networked embedded systems using the smart device and fieldbus technologies are now found in many industrial fields including process automation and automobiles. However the discrepancy between a node's view of current time and the rest of the system can cause many difficulties in the design and implementation of a networked system. To provide a networked system with a global reference time, the problem of clock synchronization has been intensively studied over the decades. However, many of the existing solutions, which are mainly developed for large scale distributed computer systems, cannot be directly applied to embedded systems. This paper presents a fault-tolerant clock synchronization technique that can be used for a low-cost embedded system using a CAN bus. The effectiveness of the proposed method is demonstrated with a set of microcontrollers and DC motor-based actuators.