• The Transactions of The Korean Institute of Electrical Engineers
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• v.58 no.2
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• pp.356-362
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• 2009

The ELectromagnetic Core Imperfection Detector (EL-CID) test was performed on a small generator in the laboratory and a gas turbine generator in the field to assess the fault condition of generator stator core. Artificial defects with six different sizes were introduced in the small generator. The scan results on six defects show a very large increase in the magnitude of fault current compared to that obtained with a healthy core. After the stator core heats up, a thermal imaging camera was used to detect hot spot on the inner surface of the core for comparison. Several faults were found during inspection of the gas turbine generator with the EL-CID. It has been shown that the existence of a fault can be determined by monitoring the magnitude of fault current.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.54 no.6
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• pp.267-273
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• 2005

This paper proposes a line-to-ground fault location algorithm for underground cable system. A feature of the proposed method is a new algorithm based on the analytic research which has not been tried until now. The proposed method firstly makes voltage and current equations using analysis of distributed parameter circuit for each of cores and sheathes respectively, and then establishes an equation of the fault distance according to the analysis of the fault conditions. Finally the solution of this equation is calculated by Newton-Raphson iteration method. The effectiveness of this proposed algorithm has been proven through PSCAD/EMTDC(Ver. 4.1) simulations.

• Proceedings of the KIEE Conference
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• 2004.11b
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• pp.24-27
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• 2004

This paper proposes a new algorithm of underground cable fault location based on the analysis of distributed parameter circuit. The proposed method firstly makes voltage and current equations for each of cores and sheathes respectively, and then establishes an equation of the fault distance according to the analysis of the fault conditions. Finally the solution of this equation is calculated by Newton-Raphson iteration method. The effectiveness of this proposed algorithm has been proven through PSCAD/EMTDC simulations.

• The Journal of Engineering Geology
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• v.26 no.2
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• pp.187-196
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• 2016

We conducted three-dimensional finite element analysis to predict the presence of upcoming fault zones during tunneling. The analysis considered longitudinal displacements measured at tunnel face, and used 28 numerical models with various fault attitudes. The x-MR (moving range) control chart was used to analyze quantitatively the effects of faults distributed ahead of the tunnel face, given the occurrence of a longitudinal displacement. The numerical models with fault were classified as fault gouge, fault breccia, and fault damage zones. The width of fault cores was set to 1 m (fault gouge 0.5 m and fault breccia 0.5 m) and the width of fault damage zones was set to 2 m. The results, suggest that fault centers could be predicted at 2~26 m ahead of the tunnel face and that faults could be predicted earliest in the 45° dip model. In addition, faults could be predicted earliest when the angle between the direction of tunnel advance and the strike of the fault was smallest.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.5
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• pp.717-722
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• 2016

In this paper, in order to support the peak current limiting function depending on the intensity of the fault current at the early stage of failure, a two magnetically coupled type superconducting fault current limiter (SFCL) is proposed, which includes high-Tc superconducting (HTSC) element 1, where the existing primary and secondary coils are connected to one iron core in parallel, and HTSC element 2, which is connected to the tertiary winding using an additional iron core. The results of the experiments in this study confirmed that the two magnetic coupling type SFCL having coil 1 and coil 2 connected in parallel using dual iron cores is capable of having only HTSC element 1 support the burden of the peak current when a failure occurs. The reason for this is that although HTSC element 1 was quenched and malfunctioned because the instantaneous factor of the initial fault current was large, the current flowing to coil 3 did not exceed the critical current, which would otherwise cause HTSC element 2 to be quenched and not function. In order to limit the peak current upon fault through the sequential HTSC elements, the design should allow it to have the same value as the low value of coil 1 while having coil 3 possess a higher self-inductance value than coil 2. In addition, a short-circuit simulation experiment was conducted to examine and validate the current limiting and recovery characteristics of the SFCL when the winding ratio between coil 1 and coil 2 was 0.25. Through the analysis of the short-circuit tests, the current limiting and recovery characteristics in the case of the additive polarity winding was confirmed to be superior to that of the subtractive polarity winding.

• ETRI Journal
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• v.30 no.3
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• pp.403-411
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• 2008

This paper introduces an interconnect delay fault test (IDFT) controller on boards and system-on-chips (SoCs) with IEEE 1149.1 and IEEE 1500 wrappers. By capturing the transition signals launched during one system clock, interconnect delay faults operated by different system clocks can be simultaneously tested with our technique. The proposed IDFT technique does not require any modification on boundary scan cells. Instead, a small number of logic gates needs to be plugged around the test access port controller. The IDFT controller is compatible with the IEEE 1149.1 and IEEE 1500 standards. The superiority of our approach is verified by implementation of the controller with benchmark SoCs with IEEE 1500 wrapped cores.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.11
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• pp.109-118
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• 2007

As the integration density and the operating speed of System on Chips (SoCs) become increasingly high, it is crucial to test delay defects on the SoCs. This paper introduces an enhanced IEEE 1500 wrapper cell architecture and IEEE 1149.1 TAP controller for the wrapper interface logic, and proposes a transition delay fault test method. The method proposed can detect slow-to-rise and slow-to-fall faults sequentially with low area overhead and short test time. and simultaneously test IEEE 1500 wrapped cores operating at different core clocks.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.9
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• pp.45-54
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• 2002

This paper proposes serial test data compression, a novel DFT scheme for embedded cores in SOC. To reduce test data amounts, share bit compression and fault undetectable fault pattern compression techniques was used. A Circuits using serial test data compression method are derived from a scan DFT method including a test-per-clock technique. For an experiment of the proposed compression method, full scan versions of ISCASS85 and ISCASS89 were used. ATALANTA has been used for ATPG and fault simulation. The amount of test data has been reduced by maximum 98% comparing with original data.

• Proceedings of the Korean Geotechical Society Conference
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• 2002.03a
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• pp.63-70
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• 2002

In tunnel construction, the information on the rock quality and the location of fault or fracture are crucial for economical design of support pattern and for safe construction of the tunnel. The grade of rock is commonly estimated through the observation with the naked eye of recovered cores in drilling or from physical parameters obtained by their laboratory test. Since drilling cost is quite expensive and terrains of planned sites for tunnel construction are rough in many cases, however, only limited information could be provided by core drilling Electrical resistivity and EM surveys may be a clue to get over this difficulty. Thus we have investigated electrical resistivity and EM field data providing regional Information of the rock Quality and delineating fault and fracture over a rough terrain. In this paper, we present some case histories using electrical resistivity and EM survey for the site investigation of tunnel construction. Through electrical resistivity and EM survey, the range and depth of coal seam was clearly estimated, cavities were detected in limestone area, and weak zones such as joint, fault and fracture have been delineated.

• The Journal of Engineering Geology
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• v.27 no.1
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• pp.9-20
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• 2017

To date, several studies have been carried out to partially compare and analyze the resistivity values within the Yangsan fault zone through the electrical resistivity survey of the exposed fault zone. However, it is not easy to directly observe a large scaled fault like Yangsan fault that has been weathered, especially due to the weathering of the fault core. This study aimed to reveal the characteristics of location, geometry, the fault core zone as well as underground distribution of the associated fault damage zone, based on the results of electrical resistivity and micro-topographic surveys as well as field geology survey in the southern Yangsan fault zone (Eonyang area). The resistivity anomaly zones developed in the NNE to NE direction were confirmed by the electrical resistivity survey. According to the electrical resistivity, micro-topographic, and field geologic surveys, the Yangsan fault has been formed by three to five fault cores, fault damage zones and/or fractured zones.