• Title/Summary/Keyword: Fault Tolerance

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FAULT-TOLERANT DESIGN FOR ADVANCED DIVERSE PROTECTION SYSTEM

  • Oh, Yang Gyun;Jeong, Kin Kwon;Lee, Chang Jae;Lee, Yoon Hee;Baek, Seung Min;Lee, Sang Jeong
    • Nuclear Engineering and Technology
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    • v.45 no.6
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    • pp.795-802
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    • 2013
  • For the improvement of APR1400 Diverse Protection System (DPS) design, the Advanced DPS (ADPS) has recently been developed to enhance the fault tolerance capability of the system. Major fault masking features of the ADPS compared with the APR1400 DPS are the changes to the channel configuration and reactor trip actuation equipment. To minimize the fault occurrences within the ADPS, and to mitigate the consequences of common-cause failures (CCF) within the safety I&C systems, several fault avoidance design features have been applied in the ADPS. The fault avoidance design features include the changes to the system software classification, communication methods, equipment platform, MMI equipment, etc. In addition, the fault detection, location, containment, and recovery processes have been incorporated in the ADPS design. Therefore, it is expected that the ADPS can provide an enhanced fault tolerance capability against the possible faults within the system and its input/output equipment, and the CCF of safety systems.

Fault Tolerant Operation of CHB Multilevel Inverters Based on the SVM Technique Using an Auxiliary Unit

  • Kumar, B. Hemanth;Lokhande, Makarand M.;Karasani, Raghavendra Reddy;Borghate, Vijay B.
    • Journal of Power Electronics
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    • v.18 no.1
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    • pp.56-69
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    • 2018
  • In this paper, an improved Space Vector Modulation (SVM) based fault tolerant operation on a nine-level Cascaded H-Bridge (CHB) inverter with an additional backup circuit is proposed. Any type of fault in a power converter may result in a power interruption and productivity loss. Three different faults on H-bridge modules in all three phases based on the SVM approach are investigated with diagrams. Any fault in an inverter phase creates an unbalanced output voltage, which can lead to instability in the system. An additional auxiliary unit is connected in series to the three phase cascaded H-bridge circuit. With the help of this and the redundant switching states in SVM, the CHB inverter produces a balanced output with low harmonic distortion. This ensures high DC bus utilization under numerous fault conditions in three phases, which improves the system reliability. Simulation results are presented on three phase nine-level inverter with the automatic fault detection algorithm in the MATLAB/SIMULINK software tool, and experimental results are presented with DSP on five-level inverter to validate the practicality of the proposed SVM fault tolerance strategy on a CHB inverter with an auxiliary circuit.

Remote Procedure Call Scheme to Support Fault-Tolerance (결함 허용을 제공하는 원격 프로시듀어 호출 기법)

  • Han, Suk-Jin;Koo, Yong-Wan
    • The Transactions of the Korea Information Processing Society
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    • v.2 no.4
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    • pp.453-465
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    • 1995
  • RPC(Remote Procedure Call) has been studied for programmer to easily write distributed program of little bit higher efficiency and reliability. In this study, fault-tolerant remote procedure call for hardware failures is proposed. Fault-tolerance is supplied by replicated procedures with node group, so called chain, and copies along chains are linearly ordered. Calls for procedure are sent to primary copy along chains, and other copies are propagated internally. If failures happen, first copy in faultless chain returns the result to the caller, Especially, in this study processing of redundant call message and result message, while using limited ack message, are avoided. This method supplies efficient and reliable fault-tolerance compared with existing remote procedure call.

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40-TFLOPS artificial intelligence processor with function-safe programmable many-cores for ISO26262 ASIL-D

  • Han, Jinho;Choi, Minseok;Kwon, Youngsu
    • ETRI Journal
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    • v.42 no.4
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    • pp.468-479
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    • 2020
  • The proposed AI processor architecture has high throughput for accelerating the neural network and reduces the external memory bandwidth required for processing the neural network. For achieving high throughput, the proposed super thread core (STC) includes 128 × 128 nano cores operating at the clock frequency of 1.2 GHz. The function-safe architecture is proposed for a fault-tolerance system such as an electronics system for autonomous cars. The general-purpose processor (GPP) core is integrated with STC for controlling the STC and processing the AI algorithm. It has a self-recovering cache and dynamic lockstep function. The function-safe design has proved the fault performance has ASIL D of ISO26262 standard fault tolerance levels. Therefore, the entire AI processor is fabricated via the 28-nm CMOS process as a prototype chip. Its peak computing performance is 40 TFLOPS at 1.2 GHz with the supply voltage of 1.1 V. The measured energy efficiency is 1.3 TOPS/W. A GPP for control with a function-safe design can have ISO26262 ASIL-D with the single-point fault-tolerance rate of 99.64%.

A Fault Management Architecture Using Backup FA in Hierarchical Local Registration Mobile IP (계층적 지역 등록 Mobile IP에서 백업 FA를 이용한 장애 관리 구조)

  • 임기운;홍충선;이대영
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.26 no.11C
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    • pp.1-9
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    • 2001
  • The Mobile IP protocol allows IP hosts to move between different networks without changing their IP addresses. The Mobile IP systems supporting the local registration were introduced to reduce the number of times when a home registration with the remotely located Home Agent is needed. The local registration Mobile IP protocol enhanced the performance by processing the MN\`s registration requests at a local agent. However. the local registration approach may consider other aspects of the Mobile IP systems as the FA fault tolerance. In this paper, we will briefly review previous protocols to support the FA fault tolerance in hierarchical local registration Mobile If system and will propose a fault tolerance protocol with backup FA in hierarchical local registration mobile IP t() enhance the efficiency of such systems against Foreign Agent failures.

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A Novel Fault Detection Scheme for Voltage Fed PWM Inverter (전압형 PWM 인버터의 새로운 고장 검출 기법)

  • Yu, Ok-Sun;Park, Nam-Ju;Hyun, Dong-Seok
    • The Transactions of the Korean Institute of Power Electronics
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    • v.12 no.1
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    • pp.1-8
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    • 2007
  • This paper presents a new fault detection scheme for voltage fed inverter to improve the reliability of power electronic system, which is of paramount importance in the wide industrial applications. The proposed method is achieved by using voltage across lower switches in each phase under the switch fault condition. The reconfiguration method is achieved by the four-switch topology connecting a faulty leg to the middle point of DC-link using bidirectional switches. The proposed method has a simple algorithm and fast fault detection time. Therefore, normal operation of the system after faults is continuously achieved by reconfiguration of system topology. The superior performance of the proposed fault detection and tolerance method are proved by simulation.

Fault-Tolerant Routing Algorithm in Hypercube Multicomputers (하이퍼큐브를 이용한 결함 허용 라우팅 알고리즘)

  • Choi Byung-whan;Kang Sung-soo;Rhee Chung-sei
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.30 no.5C
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    • pp.320-328
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    • 2005
  • Hypercube has a capability of fault-tolerance and regularity, which is easy to develop an algorithm. Many algorithms have been developed as an efficient fault-tolerance routing algorithm using hypercube. Among these algorithms, a method which use safe and unsafe concept was developed by Masuyama. Masuyama suggested an enhanced algorithm that take advantage of unsafe-safe concept. In this paper, we propose an algorithm that uses the unsafe, safe concept and modify Masuyama's algorithm. Using simulator we compare the performance of the proposed algorithm with existing algorithms.

Fault-tolerant Scheduling of Real-time Tasks with Energy Efficiency on Lightly Loaded Multicore Processors

  • Lee, Wan Yeon;Choi, Yun-Seok
    • International journal of advanced smart convergence
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    • v.7 no.3
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    • pp.92-100
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    • 2018
  • In this paper, we propose a fault-tolerant scheduling scheme with energy efficiency for real-time periodic tasks on DVFS-enabled multicore processors. The scheme provides the tolerance of a permanent fault with the primary-backup task model. Also the scheme reduces the energy consumption of real-time tasks with the fully overlapped execution between each primary task and its backup task, whereas most of previous methods tried to minimize the overlapped execution between the two tasks. In order to the leakage energy loss of idle cores, the scheme activates a part of available cores with rarely used cores powered off. Evaluation results show that the proposed scheme saves up to 82% energy consumption of the previous method.

Foundation Techniques and Fault-tolerance Tests of Active-Active Duplicated Domain Name Servers (Active-Active 방식의 DNS 서버의 이중화 구축 및 결함내성 시험)

  • Choi, Jae-Won
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.17 no.1
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    • pp.90-100
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    • 2013
  • Active-Standby Duplication Techniques are conventionally used for fault-tolerant systems. But in this paper we researched on the Active-Active Duplication Techniques for Fault-tolerant DNS System. Our Active-Active Duplication made the 1st DNS periodically copied to the 2nd DNS and maintained the same status by using Rsync and Crontab. Even though the 1st or the 2nd DNS stops due to some critical errors, the remaining DNS can take over and provide continuous services.

An Efficient Implementation of Tornado Code for Fault Tolerance

  • Lei, Jian-Jun;Kwon, Gu-In
    • Journal of Korea Spatial Information System Society
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    • v.11 no.2
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    • pp.13-18
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    • 2009
  • This paper presents the implementation procedure of encoding and decoding algorithms for Tornado code that can provide fault tolerance for storage and transmission system. The degree distribution satisfying heavy tail distribution is produced. Based on this distribution, a good random irregular bipartite graph is attained after plenty of trails. Such graph construction is proved to be efficient, and the experiments also demonstrate that the implementation obtains good performance in terms of decoding overhead.

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