• 한국통신학회논문지
• /
• 제32권1C호
• /
• pp.1-8
• /
• 2007

적응신호처리 분야에서 LMS(Least Mean Squar) 알고리즘은 수식이 간단하고, 적은 계산량으로 인해 널리 사용되고 있지만, 시간영역의 적응알고리즘은 입력신호의 고유치 분포폭이 넓게 분포할 때는 수렴속도가 느려지는 단점이 있다. 본 논문에서는 적응 신호처리의 수렴속도를 향상 시키고, 기존의 wavelet 변환을 고속으로 처리하는 고속화 알고리즘과 비교하여 적은 계산량으로 동일한 성능을 보이는 새로운 형태의 fast running FIR 필터 구조를 제안한다. 제안한 구조를 웨이블렛 기반 적응 알고리즘에 적용하였다. 실제로 합성 음성을 사용하여 컴퓨터 시뮬레이션을 통해 기존의 알고리즘과 비교 및 분석한 결과 제안한 알고리즘의 성능이 우수한 것을 알 수 있었다.

• 한국컴퓨터정보학회논문지
• /
• 제27권5호
• /
• pp.101-107
• /
• 2022

모델링 및 시뮬레이션은 목표 시스템의 동작 검증, 성능 분석, 운용 최적화, 예측을 위해 사용되는 기술이다. 이 기술의 대표적인 이산사건 시스템 명세(DEVS)는 모델들을 엄격한 형식론으로 정의하고 모델 간의 구조를 계층화한다. 이 DEVS 모델들의 원자 모델은 목표와 다른 의도로 동작하게 될 경우 시뮬레이션은 잘못된 의사결정으로 이어질 수 있다. 그럼에도 대부분 DEVS 시스템은 모델 테스트의 부재 또는 수동 테스트 환경으로 제공하여 개발자가 모델을 검증하는 데 오랜 시간이 소비된다. 본 논문에서는 파이썬 기반 DEVS에서 정확하고 빠른 원자 모델의 검증을 위해 스크립트 기반 테스트 시스템을 제안한다. 제안 테스트 시스템은 기존 방식인 수동 테스트와 새로운 방식인 스크립트 기반 테스트를 둘 다 사용한다. 우리 시스템의 실험 결과, 제안 테스트 방식은 스크립트를 10번 연속 실행 시 24ms 이내에 실행되었다. 그리하여 제안 시스템은 스크립트 기반 테스트를 사용해서 빠른 원자 모델 검증 시간을 보장하고, 테스트 스크립트의 재사용성을 향상한다.

• International Journal of Precision Engineering and Manufacturing
• /
• 제2권1호
• /
• pp.11-17
• /
• 2001

In drilling of composite laminates, it is important to minimize of reduce occurrences of delaminations. In particular, a peel -up delamination at entrance and push-up delamination at exit are common. Deleaminations may by avoided by regulating the drill thrust force can be controlled by adjusting the feedrate of the drill. Dynamics involved in drilling of composite laminates is time varying and nonlinear. In this paper, a fuzzy logic model and control strategy are proposed. Simulation results show that the fuzzy model can describe the nonlinear time-varying process well. The fuzzy controller realizes a fast rise time and a little overshoot of drilling force.

• 한국정보처리학회논문지
• /
• 제6권5호
• /
• pp.1203-1211
• /
• 1999

Checkpointing is the one of fault-tolerant techniques to restore faults and to restart job fast. Checkpointing algorithms in distributed systems have been studied for many years. These algorithms can be classified into synchronous Checkpointing algorithms and asynchronous Checkpoiting algorithms. In this paper, we propose an independent Checkpointing algorithm that has a minimum Checkpointing counts equal to periodic Checkpointing algorithm, and relatively short rollback distance at faulty situation. Checkpointing count is directly related to task completion time in a fault-free situation and short rollback distance is directly related to task completion time in a faulty situation. The proposed algorithm is compared with the previously proposed asynchronous Checkpointing algorithms using simulation. In the simulation, the proposed Checkpointing algorithm produces better results than other algorithms in terms of task completion time in fault-free as well as faulty situations.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 추계학술대회 논문집 전력기술부문
• /
• pp.239-241
• /
• 2003

The time domain simulation method of transient stability presents accuracy and reliability, but it demands much computational time. Therefore it is necessary to filter out very stable and very unstable cases from a large set of contingencies. Following a disturbance, the shape and magnitude of representative generator angle which is most increased after fault clearing are the measure of transient stability. This paper propose a method that is not a calculation of the exact CCT of contingency, but a fast assessment of transient stability. Also it can help operators identify transient stability immediately without analyzing the graphical results. The proposed method is applied to the KEPCO system. The PSS/E is used as a time domain simulation engine by IPLAN.

• 전력전자학회:학술대회논문집
• /
• 전력전자학회 2000년도 전력전자학술대회 논문집
• /
• pp.339-342
• /
• 2000

Repetitive Load Prediction is proposed for the UPS inverter application of the second order deadbeat controller which is robust against the calculation time delay and the parameter variation and which gets fast response against the load variation. The proposed technique predicts the load current ahead of two sampling time using that the load current is periodic. This is effective under nonlinear load condition. The proposed technique is derived theoretically and verified through simulation and experimental result.

• ETRI Journal
• /
• 제28권4호
• /
• pp.435-443
• /
• 2006

This paper presents an efficient carrier recovery algorithm combined with a turbo-coding technique in a mobile communication system. By using a block turbo code made up of independently decodable block codes, we can efficiently recover the fast time-varying carrier phase as well as correct channel errors. Our simulation results reveal that the proposed scheme can accommodate mobiles with high speed, and at the same time can reduce the number of iterations to lock the phase.

• 제어로봇시스템학회:학술대회논문집
• /
• 제어로봇시스템학회 1993년도 한국자동제어학술회의논문집(국내학술편); Seoul National University, Seoul; 20-22 Oct. 1993
• /
• pp.754-759
• /
• 1993

An adaptive model predictive control (AMPC) strategy using auto-regression moving-average (ARMA) models is presented. The characteristic features of this methodology are the small computer memory requirement, high computational speed, robustness, and easy handling of nonlinear and time varying MIMO systems. Since the process dynamic behaviors are expressed by ARMA models, the model parameter adaptation is simple and fast to converge. The recursive least square (RLS) method with exponential forgetting is used to trace the process model parameters assuming the process is slowly time varying. The control performance of the AMPC is verified by both comparative simulation and experimental studies on distillation column control.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2000년도 추계종합학술대회 논문집(2)
• /
• pp.83-86
• /
• 2000

This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25 $\mu\textrm{m}$ CMOS technology to realize low-jitter. We verified 50-ps of time interval within 5 clock cycles of the clock as the simulation results.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
• /
• pp.281-284
• /
• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.