• Journal of Korea Society of Industrial Information Systems
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• v.27 no.5
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• pp.25-36
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• 2022

This paper proposes a random sign reversal technique in space frequency block code for single carrier modulation. The traditional space time and frequency block coding technique may be confronted with radio environments openly, severe radio hijacking problems are to be overcome. In order to avoid such an open radio issue, random coded data protection technique for space-time block code was proposed, but this algorithm can change channel combination per an Orthogonal Frequency Division Multiplexing block. This kind of slow switching increases the probability that nearby receivers will detect the transmitted data. This paper proposes a fast switching algorithm per data symbols' basis which is a random sign reversal technique in space frequency block code for Single Carrier Modulation. It is shown in simulation that the proposed one has a superior performance in comparison with the performance of the receiver which do not know the random timing sequence of sign reversal.

• Journal of Communications and Networks
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• v.2 no.1
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• pp.58-68
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• 2000

In this paper we introduce the correlation-aided distributed sample acquisition (CDSA) scheme for fast cell search in IMT-2000 W-CDMA cellular system. The proposed scheme incorporates the state symbol correlation process into the comparison-correction based synchronization process of the original DSA scheme to enable fast acquisition even under very poor channel environment. for its realization, each mobile station (MS) has to store in its memory a set of state sample sequences. which are determined by the long-period scrambling sequences used in the system and the sampling interval of the state samples. CDSA based cell search is carried out in two stages : First, the MS first acquires the slot timing by using the primary synch code (PSC) and then identifies the igniter code which conveys the state samples of the current cell . Secondly. the MS identifies the scrambling code and frame timing by taking the comparison-correction based synchronization approach and, if the identification is not done satisfactorily within preset time. it initiates the state symbol correlation process which correlates the received symbol sequence with the pre-stored state sample sequences for a successful identification. As the state symbol SNR is relatively high. the state symbol correlation process enables reliable synchronization even in very low chip-SNR environment. Simulation results show that the proposed CDSA scheme outperforms the 3GPP 3-step approach, requiring the signal power of about 7 dB less for achieving the same acquisition time performance in low-SNR environments. Furthermore, it turns out very robust in the typical synchronization environment where large frequency offset exists.

• Journal of the Korea Society of Computer and Information
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• v.12 no.3
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• pp.185-194
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• 2007

WiBro has become intentionally standardize as IEEE 802.16e. This WiBro service has been started by a portable internet at home as well as abroad. In this paper, an offender hacker do not direct attack on system on system that It marched an attack directly in damage system because a place oneself in mobile station of portable internet WiBro and avoid to attack hacker's system. At this time, a mobile make use of network inspection policy for back-tracking based on log data. Used network log audit, and presented TCP/IP bases at log bases as used algorithm, the SWT technique that used Thumbprint Algorithm. Timing based Algorithm, TCP Sequence number. Study of this paper applies algorithm to have been progressed more that have a speed to be fast so that is physical logical complexity of configuration of present Internet network supplements a large disadvantage, and confirm an effective back-tracking system. result of research of this paper contribute to realize a back-tracking technique in ubiquitous in WiBro internet network.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.54 no.7
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• pp.299-303
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• 2005

This paper proposes an analytic method can estimate delay time considering crosstalk noise at an arbitrary node of RC-class interconnects under saturated ramp input using a simple closed-form expression. In the case of single interconnects, algebraic expression presented in existent research can estimate delay time under ramp input using delay time under step input, and we applied it to estimate delay time considering crosstalk noise. As the result, we can provide a intuitive analysis about signal integrity of circuits that include crosstalk noise reducing computational complexity significantly.

• Journal of Positioning, Navigation, and Timing
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• v.12 no.3
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• pp.215-228
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• 2023

The State Space Representation (SSR) method provides individual corrections for each Global Navigation Satellite System (GNSS) error components. This method can lead to less bandwidth for transmission and allows selective use of each correction. Precise Point Positioning (PPP) - Real-Time Kinematic (RTK) is one of the carrier-based precise positioning techniques using SSR correction. This technique enables high-precision positioning with a fast convergence time by providing atmospheric correction as well as satellite orbit and clock correction. Currently, the positioning service that supports PPP-RTK technology is the Quazi-Zenith Satellite System Centimeter Level Augmentation System (QZSS CLAS) in Japan. A system that provides correction for each GNSS error component, such as QZSS CLAS, requires monitoring of each error component to provide reliable correction and integrity information to the user. In this study, we conducted an analysis of the performance of residual error bounding for each error component. To assess this performance, we utilized the correction and quality indicators provided by QZSS CLAS. Performance analyses included the range domain, dispersive part, non-dispersive part, and satellite orbit/clock part. The residual root mean square (RMS) of CLAS correction for the range domain approximated 0.0369 m, and the residual RMS for both dispersive and non-dispersive components is around 0.0363 m. It has also been confirmed that the residual errors are properly bounded by the integrity parameters. However, the satellite orbit and clock part have a larger residual of about 0.6508 m, and it was confirmed that this residual was not bounded by the integrity parameters. Users who rely solely on satellite orbit and clock correction, particularly maritime users, thus should exercise caution when utilizing QZSS CLAS.

• The KIPS Transactions:PartA
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• v.10A no.3
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• pp.247-254
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• 2003

This paper describes a Delay Locked Loop (DLL) with low supply voltage and wide lock range for Synchronous DRAM which employs Double Data Rate (DDR) technique for faster data transmission. To obtain high resolution and fast lock-on time, a new type of phase detector is designed. The new counter and lock indicator structure are suggested based on the Dual-clock dual-data Flip Flop (DCDD FF). The DCDD FF reduces the size of counter and lock indicator by about 70%. The delay line is composed of coarse and fine units. By the use of fast phase detector, the coarse delay line can detect minute phase difference of 0.2 nsec and below. Aided further by the new type of 3-step vernier fine delay line, this DLL circuit achieves unprecedented timing resolution of 25psec. This DLL spans wide locking range from 500MHz to 500MHz and generates high-speed clocks with fast lock-on time of less than 5 clocks. When designed using 0.25 um CMOS technology with 1.8V supply voltage, the circuit consumes 32mA at 500MHz locked condition. This circuit can be also used for other applications as well, such as synchronization of high frequency communication systems.

• Journal of Mechanical Science and Technology
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• v.19 no.5
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• pp.1194-1205
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• 2005

The common-rail injection systems, as a new diesel injection system for passenger car, have more degrees of freedom in controlling both the injection timing and injection rate with the high pressure. In this study, a piezo-driven injector was applied to a high pressure common-rail type fuel injection system for the control capability of the high pressure injector's needle and firstly examined the piezo-electric characteristics of a piezo-driven injector. Also in order to analyze the effect of injector's needle response driven by different driving method on the injection, we investigated the diesel spray characteristics in a constant volume chamber pressurized by nitrogen gas for two injectors, a solenoid-driven injector and a piezo-driven injector, both equipped with the same injection nozzle with sac type and 5-injection hole. The experimental method for spray visualization was based on back-light photography technique by utilizing a high speed framing camera. The macroscopic spray propagation was geometrically measured and characterized in term of the spray tip penetration, spray cone angle and spray tip speed. For the evaluation of the needle response of the above two injectors, we indirectly estimated the needle's behavior with an accelerometer and injection rate measurement employing Bosch's method was conducted. The experimental results show that the spray tip penetrations of piezo­driven injector were longer, on the whole, than that of the solenoid-driven injector. Besides we found that the piezo-driven injector have a higher injection flow rate by a fast needle response and it was possible to control the injection rate slope in piezo-driven injector by altering the induced current.

• Journal of Broadcast Engineering
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• v.17 no.2
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• pp.374-387
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• 2012

In this paper, we implement a new hardware for finding the significant coefficients of a digital hologram and ciphering them using discrete wavelet packet transform (DWPT). Discrete wavelet transform (DWT) and packetization of subbands is used, and the adopted ciphering technique can encrypt the subbands with various robustness based on the level of the wavelet transform and the threshold of subband energy. The hologram encryption consists of two parts; the first is to process DWPT, and the second is to encrypt the coefficients. We propose a lifting based hardware architecture for fast DWPT and block ciphering system with multi-mode for the various types of encryption. The unit cell which calculates the repeated arithmetic with the same structure is proposed and then it is expanded to the lifting kernel hardware. The block ciphering system is configured with three block cipher, AES, SEED and 3DES and encrypt and decrypt data with minimal latency time(minimum 128 clocks, maximum 256 clock) in real time. The information of a digital hologram can be hided by encrypting 0.032% data of all. The implemented hardware used about 200K gates in $0.25{\mu}m$ CMOS library and was stably operated with 165MHz clock frequency in timing simulation.