• 한국철도학회:학술대회논문집
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• 한국철도학회 2009년도 춘계학술대회 논문집 특별세미나,특별/일반세션
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• pp.623-628
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• 2009

There is an increasing demand for efficient high power/weight auxiliary power supplies for use on high speed traction application. Many new conversion techniques have been proposed to reduce the voltage and current stress of switching components, and the switching losses in the traditional pulse width modulation(PWM) converter. Especially, the phase shift full bridge zero voltage switching PWM techniques are thought most desirable for many applications because this topology permits all switching devices to operate under zero voltage switching(ZVS) by using circuit parasitic components such as leakage inductance of high frequency transformer and power device junction capacitance. The proposed topology is found to have higher efficiency than conventional soft-switching converter. Also it is easily applicable to phase shift full bridge converter by applying an energy recovery snubber consisted of fast recovery diodes and capacitors.

• 한국철도학회:학술대회논문집
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• 한국철도학회 2008년도 추계학술대회 논문집
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• pp.321-324
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• 2008

Recently, there is an increasing demand for efficient high power/weight auxiliary power supplies for use on high speed traction application. many new conversion techniques have been proposed to reduce the voltage and current stress of switching components, and the switching losses in the traditional pulse width modulation(PWM) converter. Among them, the phase shift full bridge zero voltage switching PWM techniques are thought most desirable for many applications because this topology permits all switching devices to operate under zero voltage switching(ZVS) by using circuit parasitic components such as leakage inductance of high frequency transformer and power device junction capacitance. The proposed topology is found to have higher efficiency than conventional soft-switching converter. Also it is easily applicable to phase shift full bridge converter by applying an energy recovery snubber consisted of fast recovery diodes and capacitors.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1999년도 하계학술대회 논문집 G
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• pp.3129-3131
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• 1999

The electronic ballast for MHD lamp was studied for automotive headlight application. Its basic principle is the Current Sourcing Push-Pull Resonant Inverter with DC I2Volt input Voltage. By changing the switching frequency according to the lamp state, the automotive requirement of very fast warm-up and the zero voltage switching condition were shown by the simulation of the ballast circuit.

• 전력전자학회논문지
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• 제17권4호
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• pp.368-376
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• 2012

According to developed distributed generators, Solid State Circuit Breaker(SSCB) is essential for high power quality of DC Grid. In this paper, a simple and new structure of DC SSCB with a fast circuit breaker and fault current limiter is proposed. It can help to choice low specification of elements because of the limiting of fault current and achieve economic efficiency for minimizing auxiliary SCRs. Also all of SCRs have little switching loss because they operate under ZVS and ZCS. Through simulations and experiments of short-circuit fault, the performance characteristic of proposed circuit is verified and a guideline is so suggested that the DC SSCB is applied for a different DC grid using formulas.

• 대한전기학회논문지
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• 제43권5호
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• pp.761-769
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• 1994

VCB (Vacuum Circuit Breaker), with the strong arc extinction capability in switching the source of an induction motor, occurs the severe switching surge voltage which can cause the breakdown or the deterioration of motor insulation. Therefore, a method which reduces surge voltage across motor windings is necessary. So, it is analyzed that fast-rise-time surges resulting from VCB switching operations give rise to severe voltage stress on turn insulation. Additionally, the switching surge simulation algorithms using EMTP are developed, and C, R values of surge suppressor minimizing the steep-fronted stress in winding insulation surges are calculated.

• 대한전자공학회논문지SD
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• 제43권12호
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• pp.23-32
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• 2006

다층 고속 디지털 보드에 대한 빠르고 정확한 전압 버스 설계 방법은 정확하고 정밀한 고속 보드에 전원 공급망 설계 방법을 위해 고안되었다. FAPUD는 PBEC(Path Based Equivalent Circuit)모델과 망 합성 방법의 두 중요 알고리즘을 기반으로 구성된다. PBEC 모델 기반의 회로 레벨의 2차원 전원 분배 망의 전기적 값으로부터 lumped 1차원 회로 모델로 간단한 산술 표현들을 활용한다 제안된 PBEC 기반인 회로 단계 설계는 제안한 지역 접근법을 이용해 수행된다. 이 회로 단계 설계는 온칩 디커플링 커패시터의 크기, 오프칩 디커플링 커패시터의 위치와 크기, 패키지 전압 버스의 유효한 인덕턴스를 직접 결정하고 계산한다. 설계 출력에 따라 모든 디커플링 커패시터가 포한된 lumped 회로 모델과 전압 버스의 레이아웃은 FAPUD 방법을 이용한 후 얻을 수 있다. 미세조정 과정에서, I/O Switching에 의해 덧붙여진 Simultaneous Switching Noise(SSN)를 고려한 보드 재 최적화가 수행될 수 있다 이는 전원 공급 잡음에 I/O 동작 효과가 lumped 회로 모델을 가지고 전 동작 주파수 범위에 대해 추산될 수 있기 때문이다. 게다가 만약 설계에 조정이 필요하거나 교체해야 한다면, FAPUD 방법은 다른 전면 설계변경 없이 디커플링 커패시터들을 대체하여 설계를 수정하는 것이 가능하다. 마지막으로 FAPUD 방법은 전형적인 PEEC 기본설계 방법과 비교해 정확하고 FAPUD 방법의 설계 시간은 전형적인 PEEC 기본 설계 방법의 시간보다 10배가 빠르다.

• 전력전자학회논문지
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• 제8권5호
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• pp.389-396
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• 2003

직류진원 장치의 부하에 단락이 발생하는 경우 직류전원을 부하로부터 신속히 차단하고 재인가 가능한 새로운 방식의 ac/dc 컨버터를 제안하였다. 제안한 방식의 컨버터 출력전윈은 부하단락시 차단 및 정상상태로 회복시 직류전원을 재인가하여 정격출력전압으로 확립되는데 소요되는 시간이 각각 수백 $\mu\textrm{s}$ 이내에 이루어지는 특징이 있다. 또한 컨버터 출력필터 커패시터는 부하가 단락된 상태에서도 방전하지 않고 거의 정격출력전압을 유지할 수 있으므로 직류전원을 단락상태가 소멸된 정상부하에 재인가시 전압의 오버슈트 없이 신속한 부하전압 확립이 가능하다. 제안한 방식의 컨버터는 기존 방식에 비해 구조가 간단하고 소형경량화 가능한 장점이 있다. 제안한 회로방식에 대한 동작원리 설명 및 특성해석을 하였으며 실험을 통하여 그 유용성을 입증하였다.

• 대한전기학회논문지:전기기기및에너지변환시스템부문B
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• 제53권5호
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• pp.351-357
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• 2004

In this paper, we present an analytical method that provides fast and efficient evaluation of the conversion efficiency for switching power supplies. In the proposed method, the conduction losses are evaluated by calculating the effective values of the ideal current waveform first and incorporating them into an exact equivalent circuit model of the switching power supply that includes all the parasitic resistances of the circuit components. While the winding losses and core losses are accurately accounted for the magnetic components, the skin and proximity effects are assumed to be negligible in order to simplify the analysis. The validity and accuracy of the proposed method are verified with experiments on a prototype active-clamped forward converter with synchronous rectification. An excellent correlation between the experiments and theories are obtained for the input voltages of 36-75 V with 4-6 MOSFETs employed for the synchronous rectification.

• Journal of Power Electronics
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• 제18권4호
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• pp.1255-1267
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• 2018

Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.

• Journal of Power Electronics
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• 제17권3호
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• pp.601-609
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• 2017

Gallium nitride (GaN) power switching devices are promising candidates for high switching frequency and high efficiency power conversion due to their fast switching, low on-state resistance, and high-temperature operation capability. In order to facilitate the use of these new devices better, it is required to investigate the device characteristics and performance in detail preferably by comparing with various conventional silicon (Si) devices. This paper presents a comprehensive study of GaN high electron mobility transistor (HEMT) based non-isolated point-of-load (POL) synchronous buck converter operating at 2.7 MHz with a high step-down ratio (24 V to 3.3 V). The characteristics and performance of GaN HEMT and three different Si devices are analytically investigated and the optimal operating point for GaN HEMT is discussed. Zero-voltage switching (ZVS) is implemented to minimize switching loss in high switching frequency operation. The prototype circuit and experimental data support the validity of analytical and simulation results.