• The Journal of the Korea Contents Association
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• v.3 no.2
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• pp.11-18
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• 2003

In this paper, we propose a fast variable block matching algorithm for motion estimation based on bit-patterns. Motion estimation in the proposed algorithm is peformed after the representation of image sequence is transformed 8-bit pixel values into 1-bit ones by the mean pixel value of search block, which brings a short searching time by reducing the computational complexity. Moreover, adaptive searching methods according to the motion information of the block make the procedure of motion estimation efficient by eliminating unnecessary searching processes of low motion block and deepening a searching procedure in high motion block. Experimental results show that the proposed algorithm provides bettor performance - average 0.5dB PSNR improvement and about 99% savings in the number of operations - than full search Hock matching algorithm with a fixed block size.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.211-214
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• 2001

This paper presents an efficient fast motion estimation algorithm and image segmentation method for low bit-rate coding. First, with region split information, the algorithm splits the image having homogeneous and semantic regions like face and semantic regions in image. Then, in these regions, We find the motion vector using adaptive search window adjustment. Additionally, with this new segment based fast motion estimation, we reduce blocking artifacts by intensively coding our interesting region(face or arm) in input image. The simulation results show the improvement in coding performance and image quality.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.823-824
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• 2008

In this paper, we propose a robust and fast digital image stabilization algorithm based on edge detection. The proposed algorithm exploits sobel operator to obtain edge image and fast detects irregular conditions with analyzing an edge information of the image. Experimental results show that the proposed algorithm can gain better performance in the sense of speed and precision comparing with full-block search method.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.01a
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• pp.512-515
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• 2009

A 90-nm CMOS motion estimation (ME) processor was developed by employing dynamic voltage and frequency scaling (DVFS) to greatly reduce the dynamic power. To make full use of the advantages of DVFS, a fast ME algorithm and a small on-chip DC/DC converter were also developed. The fast ME algorithm can adaptively predict the optimum supply voltage ($V_D$) and the optimum clock frequency ($f_c$) before each block matching process starts. Power dissipation of the ME processor, which contained an absolute difference accumulator as well as the on-chip DC/DC converter and DVFS controller, was reduced to $31.5{\mu}W$, which was only 2.8% that of a conventional ME processor.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.1
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• pp.49-55
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• 2007

To improved the multi-resolution fast hierarchical motion estimation by using de-interlacing algorithm that is effective in term of both performance and VLSI implementation, is proposed so as to cover large search area field-based as well as frame based image processing in SoC design. In this paper, we have simulated a various picture mode M=2 or M=3. As a results, the proposed algorithm achieved the motion estimation performance PSNR compare with the full search block matching algorithm, the average performance degradation reached to -0.7dB, which did not affect on the subjective quality of reconstructed images at all. And acquiring the more desirable to adopt design SoC for the fast hierarchical motion estimation, we exploit foreground and background search algorithm (FBSA) base on the dual arithmetic processor element(DAPE). It is possible to estimate the large search area motion displacement using a half of number PE in general operation methods. And the proposed architecture of MHME improve the VLSI design hardware through the proposed FBSA structure with DAPE to remove the local memory. The proposed FBSA which use bit array processing in search area can improve structure as like multiple processor array unit(MPAU).

• The Journal of the Acoustical Society of Korea
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• v.16 no.2
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• pp.95-100
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• 1997

In this paper, we present a new fast VQ encoding algorithm. The proposed algorithm facilitates two characteristics of a vector, i.e., mean and variance to reject many unlikely codewords and save a lot of computation time. Since the proposed algorithm, which is based upon geometric considerations, rejects those codewords that are impossible to be the closest codeword, it provides the same results as a conventional exhaustive(or full) search algorithm. The simulation results confirm the effectiveness of the proposed algorithm.

• Proceedings of the Korea Information Processing Society Conference
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• 2006.05a
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• pp.153-156
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• 2006

본 논문에서는 H.264 표준화 기구인 Joint Video Team(JVT) 권고안의 정수 단위 화소 움직임 예측을 위한 Unsymmetrical-cross Multi-Hexagon-grid Search(UMHexagonS) 알고리즘에서 Uneven Multi-Hexagon-grid Search(UMHGS) 부분을 개선한 알고리즘을 제안한다. 제안하는 알고리즘은 이전 프레임의 동일위치 또는 상위 모드에서 이미 선택된 움직임 벡터(MV: Motion Vector)를 이용하여 신호 대 잡음 비(PSNR: Peak Signal to Noise Ratio) 및 평균 비트 율(Average Bitrates)을 유지하면서, 현재 매크로블록의 검색영역을 줄이는 것이 가능하다. 제안하는 알고리즘의 성능은 Full Search Block Matching Algorithm(FSBMA) 및 UMHexagonS 알고리즘의 integer pel 에 대한 SAD(Sum of Absolute Difference) 연산횟수로 비교평가 하였다. 그 결과, FSBMA 에 비하여 평균 97.64%, UMHexagonS 에 비하여는 평균 17.48%의 연산횟수를 감소시키는 우수함을 보였다.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.903-904
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• 2008

This paper suggests a simple scheme of block motion estimation in which the search pattern selection is based on the classification of motion content available in the spatio temporal neighboring blocks. The search area is divided into eight sectors and the search pattern selection is also based on the direction of predicted motion vector. Experimental results show that the proposed algorithm has achieved good predicted image quality measured in terms of PSNR and has very less computational complexity.

• ETRI Journal
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• v.32 no.4
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• pp.638-641
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• 2010

With the growth of memory capacity and density, memory testing and repair with the goal of yield improvement have become more important. Therefore, the development of high efficiency redundancy analysis algorithms is essential to improve yield rate. In this letter, we propose an improved built-in redundancy analysis (BIRA) algorithm with a minimized binary search tree made by simple calculations. The tree is constructed until finding a solution from the most probable branch. This greatly reduces the search spaces for a solution. The proposed BIRA algorithm results in 100% repair efficiency and fast redundancy analysis.

• The Journal of the Korea Contents Association
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• v.11 no.5
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• pp.9-14
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• 2011

This paper presents a new fast motion estimation method where search ranges are determined by the probabilities of motion vector differences (MVDs), which is an adaptive/dynamic search range (ASR) method. The MVDs' distribution is investigated and its parameter is estimated by the maximum likelihood estimator. With the estimated distribution, we show that the search ranges can be efficiently restricted by a prefixed probability for MVDs. Experimental results showed that the performance of the proposed method is very similar to that of the full search algorithm in PSNR but it enables significant reduction in the computational complexity. In addition, they revealed that the proposed method determine the search ranges much more efficiently than the conventional ASR methods.