• Proceedings of the KIEE Conference
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• 2002.07a
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• pp.566-567
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• 2002

In this study, the measurement part in which the Fast Fourier Transform module and orthogonal filter are included is proposed. Protection relay should has a high precision and concurrently real-time response. Because FFT routine give micro-processor heavy burden and orthogonal filter reduces precision, both FFT module and orthogonal filter are designed to have different sampling frequency.

• International Journal of Internet, Broadcasting and Communication
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• v.11 no.2
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• pp.27-30
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• 2019

Factory monitoring systems are gaining importance in wide areas of industry. Especially, there have been many efforts in implementation of vibration measurement and analysis for monitoring the status of rotating machines. In this paper, a digital signal processor (DSP) based monitoring system dedicated to the vibration monitoring and analysis on rotating machines is discussed. Vibration signals are acquired and processed for the continuous monitoring of the machine status. Time domain signals and fast Fourier transform (FFT) are used for vibration analysis. All of the signal processing procedures are done in the DSP to reduce the production and maintenance cost. The developed system could also provide remote and mobile monitoring capabilities to operator via internet connection. This paper describes the overview of the functional blocks of the implemented system. Test results based on signals from small-size single phase motors are discussed for monitoring and defect diagnosis of the machine status.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.42 no.2 s.302
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• pp.143-150
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• 2005

This paper proposes a new $radix-2^4$ FFT algorithm and an efficient pipeline architecture based on this new algorithm for OFDM systems. The pipeline architecture based on the new algorithm has the same number of multipliers as that of the $radix-2^2$ algorithm. However, the multiplier complexity could be reduced by more than $30\%$ by replacing one half of the programmable complex multipliers by the newly proposed CSD constant complex multipliers. From synthesis simulations of a standard 0.35um CMOS Samsung process, a proposed CSD constant complex multiplier achieved more than $60\%$ area efficiency when compared with the conventional programmable complex multiplier. This promoted efficiency can be used for the design of a long length FFT processor in wireless OFDM applications which needs more power and area efficiency.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.93-98
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• 2003

With the improvement of digital signal processors, digital pulse compressor(DPC) is widely used in radar systems. The DPC can be implemented by using FIR filter algorithm in time domain or FFT algorithm in frequency domain. This paper designs an expansible DPC using multiple DSPs. With ADSP-21060 of Analog Devices Inc., the computation time as a function of the number of received range cells and FIR filter tap is compared and analyzed in time domain using C-language and assembly language. therefore, when radar system parameters are determined, the number of DSP's required to implement DPC can be easily estimated.

• Journal of the Optical Society of Korea
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• v.19 no.4
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• pp.334-339
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• 2015

Terabit-per-second (Tb/s) transmission capacity for the next generation of long-haul communication networks can be achieved using multicarrier optical super-channel technology. In an elastic orthogonal frequency division multiplexing (OFDM) super-channel transmission system, demultiplexing a portion of an entire spectrum in the form of a subband with minimum power is critically required. A major obstacle to achieving this goal is the analog-to-digital converter (ADC), which is power-hungry and extremely expensive. Without a proper ADC that can work with low power, it is unrealistic to design a 100G coherent receiver suitable for a commercially deployable optical network. Discrete Fourier transform (DFT) is often seen as a primary technique for understanding partial demultiplexing, which can be attained either optically or electronically. If fairly comparable performance can be achieved with an all-optical DFT circuit, then a solution independent of data rate and modulation format can be obtained. In this paper, we investigate two distinct OFDM super-channel receiver models, based on electronic and all-optical DFT-technologies, for partial carrier demultiplexing in a multi-Tb/s transmission system. The performance comparison of the receivers is discussed in terms of bit-error-rate (BER) performance.

• Journal of Power Electronics
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• v.10 no.4
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• pp.412-418
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• 2010

This paper proposes a new algorithm to generate a reference signal for an active power filter using a sliding-window FFT operation to improve the steady-state performance of the active power filter. In the proposed algorithm the sliding-window FFT operation is applied to the load current to generate the reference value for the compensating current. The magnitude and phase-angle for each order of harmonics are respectively averaged for 14 periods. Furthermore, the phase-angle delay for each order of harmonics passing through the controller is corrected in advance to improve the compensation performance. The steady-state and transient performance of the proposed algorithm was verified through computer simulations and experimental work with a hardware prototype. A single-phase active power filter with the proposed algorithm can offer a reduction in THD from 75% to 4% when it is applied to a non-linear load composed of a diode bridge and a RC circuit. The active power filter with the proposed reference generation method shows accurate harmonic compensation performance compared with previously developed methods, in which the THD of source current is higher than 5%.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.45 no.3
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• pp.103-110
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• 2008

In this paper, an efficient butterfly structure for 8K/2K-Point Radix-4 FFT algorithm using CORDIC(coordinate rotation digital computer) is proposed. It is shown that CORDIC can be efficiently used in twiddle factor calculation of the Radix-4 FFT algorithm. The Verilog-HDL coding results for the proposed CORDIC butterfly structure show 36.9% cell area reduction comparison with those of the conventional multiplier butterfly structure. Furthermore, the 8K/2K-point Radix-4 pipeline structure using the proposed butterfly and delay commutators is compared with other conventional structures. Implementation coding results show 11.6% cell area reduction. Due to its efficient processing scheme, the proposed FFT structure can be widely used in large size of FFT like OFDM Modem.

• Journal of Korea Society of Digital Industry and Information Management
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• v.5 no.4
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• pp.127-137
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• 2009

This paper is proposed that in-output Digital module is acquired a vibration signal of a rotating machinery by Data Acquisition System. The module is designed to get ride of nose through low pass filter on the vibration signal from sensors and set the gain value for being able to sampling AC to DC, and also the sampled data by sampler and the conversed data by DIP/FPGA is supplied to the analyzer for analysis at a software tool. The DIP(Digital Signal Processor) of the Digital input/output Board makes Average voltage, Peak to Peak voltage, RMS(Root Mean Square) and Gap voltage, also FFT(Fast Fourier Transform) for rotating vibration diagnosis.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.11
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• pp.1713-1719
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• 2022

As the noise canceler with a small processing delay increases the sampling frequency, a better-quality output can be obtained. For a single buffer, processing delay occurs because it is impossible to write new data while the processor is processing the data. When synthesizing with anti-noise and output signal, this processing delay creates additional buffering overhead to match the phase. In this paper, we propose an accelerator structure that minimizes processing delay and increases processing speed by alternately performing read and write operations using the Symmetric Even-Odd-buffer. In addition, we compare the structural differences between the two methods of noise cancellation (Fast Fourier Transform noise cancellation and adaptive Least Mean Square algorithm). As a result, using an Symmetric Even-Odd-buffer the processing delay was reduced by 29.2% compared to a single buffer. The proposed Symmetric Even-Odd-buffer structure has the advantage that it can be applied to various canceling algorithms.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.35-42
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• 2006

In this paper we implement a new simulator for performance analysis of a parallel digital signal processing distributed shared memory multiprocessor systems. using Parsec The key idea of this simulator is suitable in simulation of system that uses DMA function of TMS320C6701 DSP chip and local memory which have fast access time. Also, because correction of performance parameter and reconfiguration for hardware components are easy, we can analyze performance of system in various execution environments. In the simulation, FET, 2D FET, Matrix Multiplication. and Fir Filter, which are widely used DSP algorithms. have been employed. Using our simulator, the result has been recorded according to different the number of processor, data sizes, and a change of hardware element. The performance of our simulator has been verified by comparing those recorded results.