• Title/Summary/Keyword: Fast Fourier Transform algorithm

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Acoustic Radiation Analysis of Stiffened Cylindrical shell and Vibrational Velocity by FFT (보강 원통형 몰수체의 음향방사 해석과 FFT에 의한 진동 해석)

  • 배수룡;이헌곤;홍진숙
    • Proceedings of the Korean Society for Noise and Vibration Engineering Conference
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    • 1993.04a
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    • pp.128-133
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    • 1993
  • 본 연구에서는 보강 원통쉘에 대하여 주위 유체의 영향을 고려하여 진동 및 음향방사를 해석하였다. 원통셀의 운동방정식은 Donnell 이론을 적용하였으 며, Contour 적분을 풀지 않고 FFT 알고리즘(Fast Fourier Transform Algorithm)을 이용하여 원통쉘의 진동을 계산하였다. 현재까지의 방사패턴에 관한 연구는 주로 원주 방향에 집중되어 왔으나, 보강 원통쉘의 방사패턴은 원추파 모형에 가까우므로 극좌표 .theta. 방향에 대한 음향방사 패턴에 관한 연구가 이루어져야 한다. 그러므로, 본 연구에서는 극좌표에 관한 방사패턴 에 관하여 주로 고찰하였다.

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Power Quality Measurement for LED-based Green Energy Lighting Systems (LED 기반 그린에너지 조명시스템을 위한 전력품질 측정)

  • Yu, Hyung-Mo;Choi, Jin-Won;Choe, Sangho
    • Journal of the Institute of Electronics and Information Engineers
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    • v.50 no.2
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    • pp.174-184
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    • 2013
  • For the successful R&D and deployment of LED-based green energy lighting systems, the real-time power quality measurement of both various non-linear power signals including pulse waveform, spike waveform, etc and the undesired-signals including harmonics, sag, swell, etc is required. In this paper, we propose a low-cost power quality measurement (PQM) method for low- (60Hz-several KHz) to high-frequency (several tens KHz) power signals, which are generated by green-energy lighting systems, and implement a PQM testbed using TI TMS320F28335 MCU. The proposed algorithm is programmed using C in the CCS (Code Composer Studio) 3.3 environment and is verified using test signals generated by an arbitrary signal generator, NF-WF1974. In the implemented testbed, we can measure various non-linear current signals that LED SMPS generates, analyze harmonics by fast Fourier transform, and test sag, swell, and interruption using wavelet transform.

Fast Double Random Phase Encoding by Using Graphics Processing Unit (GPU 컴퓨팅에 의한 고속 Double Random Phase Encoding)

  • Saifullah, Saifullah;Moon, In-Kyu
    • Proceedings of the Korea Multimedia Society Conference
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    • 2012.05a
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    • pp.343-344
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    • 2012
  • With the increase of sensitive data and their secure transmission and storage, the use of encryption techniques has become widespread. The performance of encoding majorly depends on the computational time, so a system with less computational time suits more appropriate as compared to its contrary part. Double Random Phase Encoding (DRPE) is an algorithm with many sub functions which consumes more time when executed serially; the computation time can be significantly reduced by implementing important functions in a parallel fashion on Graphics Processing Unit (GPU). Computing convolution using Fast Fourier transform in DRPE is the most important part of the algorithm and it is shown in the paper that by performing this portion in GPU reduced the execution time of the process by substantial amount and can be compared with MATALB for performance analysis. NVIDIA graphic card GeForce 310 is used with CUDA C as a programming language.

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DC Series Arc Fault Detector Based on the Discrete Wavelet Transform Algorithm for a Large Photovoltaic System (대용량 PV 시스템 적용을 위한 DWT 알고리즘 기반 태양광 직렬 아크 검출기)

  • Cho, Chan-Gi;Ahn, Jae-Beom;Lee, Jin-Han;Ryoo, Hong-Je
    • Proceedings of the KIPE Conference
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    • 2020.08a
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    • pp.1-3
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    • 2020
  • 본 논문은 주파수 분석 방법 중 하나인 Discrete Wavelet Transform (DWT)을 활용하여 태양광 직렬 아크 사고를 검출하는 방법에 관하여 다룬다. DWT 알고리즘은 주파수 도메인에서도 시간 축 정보를 표현할 수 있어 기존의 Fast Fourier Transform (FFT) 주파수 분석 알고리즘과 차이점이 있으며, 대용량 태양광 시스템의 직렬 아크 사고 검출에 최적화 되도록 DWT 알고리즘의 속도를 향상시켜 태양광 DC 아크 사고 안전규격인 UL1699B의 요구 조건을 만족시켰다. DWT 알고리즘의 경우 TMS320F28033 기반으로 구현 되었으며 대용량 PV 시스템 적용을 위해 로고스키코일을 전류 센서로 사용하였다. 또한, 모의 DC 직렬 아크 발생 회로를 구축하여 제작한 사고 검출기의 성능을 실제 아크 발생 조건에서 검증하였다.

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The Development of Automatic Correction Algorithm for the Knocking Threshold in Spark Ignition Engine (스파크 점화기관에서의 노킹판단 기준값의 자동수정 알고리즘 개발)

  • 강성현;장광수;서정인;전광민
    • Transactions of the Korean Society of Automotive Engineers
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    • v.7 no.7
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    • pp.32-41
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    • 1999
  • In this study, a new knocking control algorithm was developed using the knock threshold value auto-correction algorithm. This algorithm uses the Fast Fourier Transform9FFT) method by measuring cylinder block vibration signals of a 1498 cc four-cylinder spark ignition engine. The experimental results show the proposed knock control algorithm provides improved performance compared to existing methods. The results also show that the proposed FFT algorithm provides real-time adjustment of the knock threshold value.

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Effective Separation Method for Single-Channel Time-Frequency Overlapped Signals Based on Improved Empirical Wavelet Transform

  • Liu, Zhipeng;Li, Lichun;Li, Huiqi;Liu, Chang
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.13 no.5
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    • pp.2434-2453
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    • 2019
  • To improve the separation performance of time-frequency overlapped radar and communication signals from a single channel, this paper proposes an effective separation method based on an improved empirical wavelet transform (EWT) that introduces a fast boundary detection mechanism. The fast boundary detection mechanism can be regarded as a process of searching, difference optimization, and continuity detection of the important local minima in the Fourier spectrum that enables determination of the sub-band boundary and thus allows multiple signal components to be distinguished. An orthogonal empirical wavelet filter bank that was designed for signal adaptive reconstruction is then used to separate the input time-frequency overlapped signals. The experimental results show that if two source components are completely overlapped within the time domain and the spectrum overlap ratio is less than 60%, the average separation performance is improved by approximately 32.3% when compared with the classic EWT; the proposed method also improves the suitability for multiple frequency shift keying (MFSK) and reduces the algorithm complexity.

An Improved PAPR Reduction Using Sub-block Phase Weighting (SPW) Method in OFDM Communication System (OFDM 시스템에서 SPW(Sub-Block Phase Weighting) 기법을 이용한 개선된 PAPR 저감 기법)

  • Kim Sun-Ae;Kang Yeong-Cheol;Suh Jae-Won;Ryu Heung-Gyoon
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.16 no.11 s.102
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    • pp.1123-1130
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    • 2005
  • In this paper, we propose an improved side information processing scheme which is important in the sub-block phase weighting(SPW) method for the peak-to-average power ratio(PAPR) reduction. SPW method is to divide the input OFDM subchannels into several subblocks and to multiply phase weighting with each subblocks, properly for the reduction of the peak power. SPW method is similar to the conventional PTS method when the number of sub-carriers, signal modulation format and the number of subblocks are the same. However, unlike the conventional PTS(Partial Transmit Sequence) and SLM(Selected Mapping) method using many stages of IFFT(Inverse Fast Fourier Transform), SPW method only needs one IFFT. Although PAPR can be reduced by SPW method, complex computation burden still remains. In this paper the flipping algorithm and the full iteration algorithm are used f3r the phase control method. Through the computer simulation, we analyze and discuss the properties and the performance of the suggested method.

Efficient Scheduling Schemes for Low-Area Mixed-radix MDC FFT Processor (저면적 Mixed-radix MDC FFT 프로세서를 위한 효율적인 스케줄링 기법)

  • Jang, Jeong Keun;Sunwoo, Myung Hoon
    • Journal of the Institute of Electronics and Information Engineers
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    • v.54 no.7
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    • pp.29-35
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    • 2017
  • This paper presents a high-throughput area-efficient mixed-radix fast Fourier transform (FFT) processor using the efficient scheduling schemes. The proposed FFT processor can support 64, 128, 256, and 512-point FFTs for orthogonal frequency division multiplexing (OFDM) systems, and can achieve a high throughput using mixed-radix algorithm and eight-parallel multipath delay commutator (MDC) architecture. This paper proposes new scheduling schemes to reduce the size of read-only memories (ROMs) and complex constant multipliers without increasing delay elements and computation cycles; thus, reducing the hardware complexity further. The proposed mixed-radix MDC FFT processor is designed and implemented using the Samsung 65nm complementary metal-oxide semiconductor (CMOS) technology. The experimental result shows that the area of the proposed FFT processor is 0.36 mm2. Furthermore, the proposed processor can achieve high throughput rates of up to 2.64 GSample/s at 330 MHz.

Detection of low frequency tonal signal of underwater radiated noise via compressive sensing (압축센싱 기법을 적용한 선박 수중 방사 소음 신호의 저주파 토널 탐지)

  • Kim, Jinhong;Shim, Byonghyo;Ahn, Jae-Kyun;Kim, Seongil;Hong, Wooyoung
    • The Journal of the Acoustical Society of Korea
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    • v.37 no.1
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    • pp.39-45
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    • 2018
  • Compressive sensing allows recovering an original signal which has a small dimension of the signal compared to the dimension of the entire signal in a short period of time through a small number of observations. In this paper, we proposed a method for detecting tonal signal which caused by the machinery component of a vessel such as an engine, gearbox, and support elements. The tonal signal can be modeled as the sparse signal in the frequency domain when it compares to whole spectrum range. Thus, the target tonal signal can be estimated by S-OMP (Simultaneous-Orthogonal Matching Pursuit) which is one of the sparse signal recovery algorithms. In simulation section, we showed that S-OMP algorithm estimated more precise frequencies than the conventional FFT (Fast Fourier Transform) thresholding algorithm in low SNR (Signal to Noise Ratio) region.

Lightweight FPGA Implementation of Symmetric Buffer-based Active Noise Canceller with On-Chip Convolution Acceleration Units (온칩 컨볼루션 가속기를 포함한 대칭적 버퍼 기반 액티브 노이즈 캔슬러의 경량화된 FPGA 구현)

  • Park, Seunghyun;Park, Daejin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.11
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    • pp.1713-1719
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    • 2022
  • As the noise canceler with a small processing delay increases the sampling frequency, a better-quality output can be obtained. For a single buffer, processing delay occurs because it is impossible to write new data while the processor is processing the data. When synthesizing with anti-noise and output signal, this processing delay creates additional buffering overhead to match the phase. In this paper, we propose an accelerator structure that minimizes processing delay and increases processing speed by alternately performing read and write operations using the Symmetric Even-Odd-buffer. In addition, we compare the structural differences between the two methods of noise cancellation (Fast Fourier Transform noise cancellation and adaptive Least Mean Square algorithm). As a result, using an Symmetric Even-Odd-buffer the processing delay was reduced by 29.2% compared to a single buffer. The proposed Symmetric Even-Odd-buffer structure has the advantage that it can be applied to various canceling algorithms.