• 한국지능시스템학회:학술대회논문집
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• 한국퍼지및지능시스템학회 2001년도 춘계학술대회 학술발표 논문집
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• pp.237-240
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• 2001

In this work, we will present an iris pattern recognition method as a biometrically based technology for personal identification and authentication. For this, we propose a new algorithm for extraction unique feature from images of the iris of the human eye and representing these feature using the discrete fourier transform. From the computational simplicity of the adopted transform, we can obtain more fast and efficient results than previous ones.

• 한국통신학회논문지
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• 제38A권12호
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• pp.1145-1147
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• 2013

FFT(Fast Fourier Transform) 알고리즘에는 DIT(Decimation-In-Time)와 DIF(Decimation-In-Frequency)가 있다. DIF 알고리즘은 Radix-2/4/8 등의 다양한 종류와 그 구현 방법이 개발되어 사용되는데 반하여 DIT 알고리즘은 순차적인 출력을 낼 수 있는 장점에도 불구하고 다양한 구현방법이 연구되지 못하였다. 이 논문에서는 DIT Radix-4 알고리즘을 유도하며 반도체 구현을 위한 효율적인 butterfly 구조를 제안한다.

• ETRI Journal
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• 제32권1호
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• pp.1-10
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• 2010

In this paper, we present a fast Fourier transform (FFT) processor with four parallel data paths for multiband orthogonal frequency-division multiplexing ultra-wideband systems. The proposed 128-point FFT processor employs both a modified radix-$2^4$ algorithm and a radix-$2^3$ algorithm to significantly reduce the numbers of complex constant multipliers and complex booth multipliers. It also employs substructure-sharing multiplication units instead of constant multipliers to efficiently conduct multiplication operations with only addition and shift operations. The proposed FFT processor is implemented and tested using 0.18 ${\mu}m$ CMOS technology with a supply voltage of 1.8 V. The hardware- efficient 128-point FFT processor with four data streams can support a data processing rate of up to 1 Gsample/s while consuming 112 mW. The implementation results show that the proposed 128-point mixed-radix FFT architecture significantly reduces the hardware cost and power consumption in comparison to existing 128-point FFT architectures.

• 전력전자학회논문지
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• 제20권1호
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• pp.72-80
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• 2015

In distributed generation systems, a grid-connected inverter should operate with synchronization to grid voltage. Considering that synchronization requires the phase angle of grid voltage, a phase locked loop (PLL) scheme is often used. The synchronous reference frame phase locked loop (SRF-PLL) is generally known to provide reasonable performance under ideal grid voltage. However, this scheme indicates performance degradation under the harmonic distorted or unbalanced grid voltage condition. To overcome this limitation, this paper proposes a phase and harmonic detection method of grid voltage using fast Fourier transform (FFT). To reduce the calculation time of FFT algorithm, minimum sampling data is taken from the voltage measurement to determine the phase angle and the magnitude of harmonic components. An experimental test setup for a grid-connected inverter system has been constructed. By comparative simulations and experiments under various abnormal grid voltage conditions, the proposed scheme has been proven to effectively track the phase angle of the grid voltage.

• 대한전기학회논문지
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• 제39권4호
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• pp.341-348
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• 1990

This paper describes an algorithm for evaluating the Loss of Load Probability (LOLP) and calculating the production cost for all the generators in the system using Fast Hartley Transform (FHT). It also suggests the deconvolution procedure which is necessary for the generation expansion planning. The FHT is as fast as or faster than the Fast Fourier Transform (FFT) and serves for all the uses such as spectral, digital processing, and convolution to which the FFT is normally applied. The transformed function using FFT has complex numbers. However, the transformed function using FHT has real numbers and the convolution become quite simple. This method has been applied for the IEEE reliability test system and practical size model system. The test results show the effectiveness of the proposed method.

• 한국통신학회논문지
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• 제24권7A호
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• pp.1005-1015
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• 1999

본 논문에서는 BPSK (binary shift keying) 방식을 사용하고 IFFT (inverse fast Fourier transform)와 FFT를 이용하여 기저 대역 변조기 및 복조기를 디지털로 구현한 MC-CDMA (multi carrier-code division multiple access) 시스템과 동일한 비트오율 (bit error rate) 성능을 갖고, 계산량과 대역폭을 줄이는 IFFT/FFT 기반의 새로운 디지털 구현 알고리즘 및 제안된 알고리즘에 적용되는 등화기 구조를 제안한다. 제안된 방법은 2개의 N/2-point 실수신호를 N/2-point IFFT와 FFT를 이용하여 동시에 변환하고 다시 복원할 수 있는 변형된 FFT 알고리즘에 기반을 두고 있다. 제안된 방법의 성능은 부가성 백색 가우시안 잡음 채널과 주파수 선택적 페이딩 채널 하에서 equal gain combiner와 maximal ratio combiner 등화기에 의한 다이버시티를 이용하여 수신했을 경우에 대한 모의실험을 통해 확인하였다.

• 사물인터넷융복합논문지
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• 제10권2호
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• pp.17-23
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• 2024

국내 상수도관의 파열, 결함 등으로 인한 누수율로 인한 손실이 매우 크고, 이런 누수를 예방을 위한 방지 대책이 필요한 상황이다. 본 논문에서는 진동 센서를 활용한 누수 탐지 센서를 개발하고 인공지능 기술을 활용한 최적의 누수 탐지 알고리듬을 제시하고자 한다. 상수도 배관에서 취득한 진동음은 FFT(Fast Fourier Transform)를 이용한 전처리 과정을 거친 뒤, 최적화된 트리 기반 부스팅 알고리듬을 적용하여 누수 분류를 하였다. 다양한 실증 환경에서 취득한 약 26만여 개의 실험 데이터에 적용한 결과 기존의 SVM(Support Vector Machine) 방법에 비해약 4%가 향상된 97%의 정확도를 얻었고, 연산 처리속도는 약 1,362배가 향상되어 엣지 디바이스 적용에도 적합함을 확인하였다.

• Journal of Electrical Engineering and Technology
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• 제12권2호
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• pp.559-568
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• 2017

Harmonic/inter-harmonic detection and analysis is an important issue in power system signal processing. This paper proposes a fast algorithm based on matching pursuit (MP) sparse signal decomposition, which can be employed to extract the harmonic or inter-harmonic components of a distorted electric voltage/current signal. In the MP iterations, the method extracts harmonic/inter-harmonic components in order according to the spectrum peak. The Fast Fourier Transform (FFT) and nonlinear optimization techniques are used in the decomposition to realize fast and accurate estimation of the parameters. First, the frequency estimation value corresponding to the maxim spectrum peak in the present residual is obtained, and the phase corresponding to this frequency is searched in discrete sinusoids dictionary. Then the frequency and phase estimations are taken as initial values of the unknown parameters for Nelder-Mead to acquire the optimized parameters. Finally, the duration time of the disturbance is determined by comparing the inner products, and the amplitude is achieved according to the matching expression of the harmonic or inter-harmonic. Simulations and actual signal tests are performed to illustrate the effectiveness and feasibility of the proposed method.

• Current Optics and Photonics
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• 제5권6호
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• pp.672-679
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• 2021

We propose a high-speed layer-based algorithm for synthesizing computer-generated holograms (CGHs), featuring sparsity-based image segmentation and computational parallelism. The sparsity-based image segmentation of layer-based three-dimensional scenes leads to considerable improvement in the efficiency of CGH computation. The efficiency enhancement of the proposed algorithm is ascribed to the field localization of the fast Fourier transform (FFT), and the consequent reduction of FFT computational complexity.

• Journal of electromagnetic engineering and science
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• 제19권1호
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• pp.6-12
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• 2019

An IE-FFT algorithm is implemented and applied to the electromagnetic (EM) solution of perfect electric conducting (PEC) scattering problems. The solution of the method of moments (MoM), based on the magnetic field integral equation (MFIE), is obtained for PEC objects with closed surfaces. The IE-FFT algorithm uses a uniform Cartesian grid to apply a global fast Fourier transform (FFT), which leads to significantly reduce memory requirement and speed up CPU with an iterative solver. The IE-FFT algorithm utilizes two discretizations, one for the unknown induced surface current on the planar triangular patches of 3D arbitrary geometries and the other on a uniform Cartesian grid for interpolating the free-space Green's function. The uniform interpolation of the Green's functions allows for a global FFT for far-field interaction terms, and the near-field interaction terms should be adequately corrected. A 3D block-Toeplitz structure for the Lagrangian interpolation of the Green's function is proposed. The MFIE formulation with the IE-FFT algorithm, without the help of a preconditioner, is converged in certain iterations with a generalized minimal residual (GMRES) method. The complexity of the IE-FFT is found to be approximately $O(N^{1.5})$and $O(N^{1.5}logN)$ for memory requirements and CPU time, respectively.