• Journal of Positioning, Navigation, and Timing
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• v.4 no.4
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• pp.161-171
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• 2015

Alternative binary offset carrier (AltBOC) signals can be approximated by four synchronized direct sequence spread spectrum (DSSS) signals, each pair of which is a quadrature phase shift keyed (QPSK) signal at a different frequency. Therefore, depending on the strength of an incoming AltBOC signal, an acquisition technique can reduce the mean acquisition time (MAT) by searching the four DSSS signals asynchronously; the search for each of the four DSSS signals can start at one of the evenly separated hypotheses on the two-dimensional hypothesis space. And detection sensitivity can be improved by multiple levels when different numbers of search results for the same hypothesis are combined. In this paper, we propose a fast AltBOC acquisition technique that has an asynchronous search strategy and efficiently utilizes the output of the four search results to increase the sensitivity level when sensitivity improvement is needed. We provide a complete theoretical analysis and demonstrate with numerous Monte Carlo simulations that the MAT of the proposed technique is much smaller than conventional AltBOC acquisition techniques.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.50 no.10
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• pp.479-485
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• 2001

In this paper, we introduce a charge pump phase-locked loop (PLL) architecture which employs a precharge phase frequency detector (PFD) and a sequential PFD to achieve a high frequency operation and a fast acquisition. Operation frequency is increased by using the precharge PFD when the phase difference is within $-{\pi}{\sim}{\pi}$ and acquisition time is shortened by using the sequential PFD and the increased charge pump current when the phase difference is larger than ${\pm}{\pi}$. So error detection range of the proposed PLL structure is not limited to $-{\pi}{\sim}{\pi}$ and a high frequency operation and a higher speed lock-up time can be achieved. The proposed PLL was designed using 1.5 ${\mu}m$ CMOS technology with 5V supply voltage to verify the lock in process. The proposed PLL shows successful acquisition for 200 MHz input frequency. On the other hand, the conventional PLL with the sequential PFD cannot operate at up to 160MHz. Moreover, the lock-up time is drastically reduced from 7.0 ${\mu}s\;to\;2.0\;{\mu}s$ only if the loop bandwidth to input frequency ratio is regulated by the divide-by-4 counter during the acquisition process. By virtue of this dual PFDs, the proposed PLL structure can improve the trade-off between acquisition behavior and locked behavior.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.1201-1204
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• 2003

This paper described a replica-delay adaptive lock-acquisition scheme for high-speed DLLs. The proposed scheme provides the fast and correct locking cycle that is variable according to the magnitude of the arbitrary replica delay (fixed delay). The scheme guarantees the wide operation range and the fast lock-aquisition time. It has been confirmed by HSPICE simulations in a 0.35${\mu}{\textrm}{m}$ CMOS process.

• Proceedings of the Korea Information Processing Society Conference
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• 2009.04a
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• pp.1352-1355
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• 2009

TCP에서 사용되는 혼잡제어(Congestion control)는 많은 이점이 있지만 그에 상응하는 단점이 존재한다. 가장 널리 사용되고 있는 TCP-Reno는 혼잡이 발생되면 혼잡 윈도우(Congestion Window)크기를 절반으로 줄이고 빠른 회복(fast recovery), 빠른 재전송(fast transmit)을 수행한다. 하지만 네트워크가 고속 네트워크로 접어들면서 효율적인 측면에서 이러한 기법들을 적용하기에는 문제가 따른다. 현재 사용되고 있는 TCP는 혼잡이 발생하면 선형적으로 점진적으로 증가 하기 때문에 많은 대역폭을 지원하는 고속 네트워크에서는 이러한 TCP의 혼잡 제어가 오히려 비 효율적이다. 본 논문에서는 이러한 문제점을 해결하기 위해 혼잡 윈도우 증가율을 추가한 혼잡제어 기법인 TCP-FBA(Fast Bandwidth Acquisition)를 제안한다.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.11
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• pp.5481-5495
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• 2018

Single pixel imaging technology has developed for years, however the video acquisition on the single pixel camera is not a well-studied problem in computer vision. This work proposes a new scheme for single pixel camera to acquire video data and a new regularization for robust signal recovery algorithm. The method establishes a single pixel video compressive sensing scheme to reconstruct the video clips in spatial domain by recovering the difference of the consecutive frames. Different from traditional data acquisition method works in transform domain, the proposed scheme reconstructs the video frames directly in spatial domain. At the same time, a new regularization called spatial cluster is introduced to improve the performance of signal reconstruction. The regularization derives from the observation that the nonzero coefficients often tend to be clustered in the difference of the consecutive video frames. We implement an experiment platform to illustrate the effectiveness of the proposed algorithm. Numerous experiments show the well performance of video acquisition and frame reconstruction on single pixel camera.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.6A
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• pp.685-692
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• 2008

In this paper, we propose a timing recovery loop for Inmarsat mini-m system downlink receiver. Inmarsat mini-m system requires a timing recovery loop which is robust in frequency offset and has fast acquisition because Inmarsat mini-m system specification requires frequency tolerance is required of ${\pm}924$ Hz (signal bandwidth: 2.4 kHz) and acquisition time of UW (Unique Word) signal duration (15ms).Therefore, we propose a timing recovery loop which is suitable for Inmarsat mini-m system. The proposed timing recovery loop adopted noncoherent UW detector and differential ELD which applied differential UW signal for stability and fast acquisition in frequency offset environment. Simulation results show that the proposed timing recovery loop has stable operation and fast acquisition in frequency offset environment for the system.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.07a
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• pp.271-274
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• 2001

In this paper, we propose a charge pump phase-locked loop (PLL) with multi-PFD which is composed of a sequential phase frequency detector(PFD) and a precharge PFD. When the Phase difference is within - $\pi$ ∼ $\pi$ , operation frequency can be increased by using precharge PFD. When the phase difference is larger than │ $\pi$ │, acquisition time can be shorten by the additional control circuit with increased charge pump current. Therefore a high frequency operation, a fast acquisition and an unlimited error detection range can be achieved.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.395-398
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• 2006

In this paper, for implementing a real-time software GNSS receiver we propose the highly efficient and fast algorithms such as partial down-conversion, phase rotator, composite I&Q accumulation, Virtual DCO technique, and parallel acquisition using FFT. When the proposed algorithms are used, more 30 tracking channels with 3 tracking arm(early-prompt-late) is operated real-time on Intel 2.8GHz personal computer. Also, the partial down-conversion reduces the FFT size, for parallel acquisition, to 1/8 of conventional FFT-size and the program size includes map is not exceed 1Mbyte. Finally, the proposed real-time software GNSS receiver using the proposed algorithms provides the navigation solution with below 10 meter rms error.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.4C
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• pp.371-376
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• 2010

In this paper, we propose a new fast carrier recovery algorithm for high-order QAM systems. The proposed algorithm detects carrier frequency offset from the phase differences among the received symbols directly and combines it with the conventional carrier recovery, so that it is possible to achieve the carrier recovery with wide tracking range and fast acquisition time. Simulation results show that the proposed carrier recovery method reduces acquisition time at large frequency offset and low signal-to-noise ratio (SNR).

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.1188-1191
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• 2003

In this paper, we focus our attention on the improvement of locking time and jitter parameter and propose the new structure of PLL which combined with the FVC, FOVI Matcher(FVC-Output and VCO-input Matching Circuit), Control Circuit and the conventional charge pump PLL. Using fast operation characteristics of the FVC, the circuit matching FVC-Output and VCO-input (FOVI Matcher) made to synchronize very fast. Fast locking time is usually required for application where the PLL has to settle rapidly if they switch from an idle mode to a normal mode and to track high-frequency data bit rate in data recovery systems. After a fast acqusition is achieved by the using the FVC, the conventional PLL operates for removing the phase error between the reference signal and the feedback signal. Therefore this structure can improve the trade-off between acquisition behavior and locked behavior.