• Title/Summary/Keyword: Fabricated design area

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Design and Implementation of Power Management Circuit for Semi-active RFID Tags (반 능동형 RFID 태그를 위한 전원 제어 회로 설계 및 구현)

  • Kim, Yeong-Kyo;Yi, Kyeon-Gil;Cho, Sung-Kyo;Nam, Ki-Hun;Kim, Shi-Ho
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.59 no.10
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    • pp.1839-1844
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    • 2010
  • A power management controller circuit with switched capacitor mode down regulator and battery charger block for semi-active RFID tags was proposed and fabricated. The main purposes of the proposed switched capacitor mode down regulator and battery charger block are to reduce standby current and to provide a self-controlled thin film battery charger by detecting the received RF power, respectively. Fabricated chip area is $360,000{\mu}m^2$ and measured standby current was about $1.3{\mu}A$. To further reduction of standby current, a wake-up circuit has to be included in the power management controller.

Design and Fabrication of Micro Patterns on Flexible Copper Clad Laminate (FCCL) Using Imprinting Process (임프린트 공정을 이용한 연성동박적층필름(FCCL)의 마이크로 패턴 제작)

  • Min, Chul Hong;Kim, Tae Seon
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.28 no.12
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    • pp.771-775
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    • 2015
  • In this paper, we designed and fabricated low cost imprinting process for micro patterning on FCCL (flexible copper clad laminate). Compared to conventional imprinting process, developed fabrication method processing imprint and UV photolithography step simultaneously and it does not require resin etch process and it can also reduce the fabrication cost and processing time. Based on proposed method, patterns with $10{\mu}m$ linewidth are fabricated on $180mm{\times}180mm$ FCCL. Compared to conventional methods using LDI (laser direct imaging) equipment that showed minimum line with $10{\sim}20{\mu}m$, proposed method shows comparable pattern resolution with very competitive price and shorter processing time. In terms of mass production, it can be applied to fabrication of large-area low cost applications including FPCB.

Micro Electrochemical Machining Using Insulated Electrode (절연 전극을 이용한 미세 전해 가공)

  • Park B.J.;Kim B.H.;Chu C.N.
    • Proceedings of the Korean Society of Precision Engineering Conference
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    • 2005.10a
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    • pp.685-688
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    • 2005
  • In the micro electrochemical machining (MECM) using ultra short pulses, the machining rate is closely related to the tool electrode area. The machining rate varies according to the machining depth or the immersion depth. When using insulated tool electrodes, those depths do not matter. In addition, micro structures with high machining depth can be fabricated because the machining characteristics do not vary with the machining depth. Another advantage of insulated electrodes is prevention of taper shape. Micro structures with high machining depth or high aspect ratio were fabricated using insulated tool electrodes.

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Design of a Built-In Current Sensor for CMOS IC Testing (CMOS 집적회로의 테스팅을 위한 새로운 내장형 전류감지 회로의 설계)

  • Hong, Seung-Ho;Kim, Jeong-Beom
    • Proceedings of the KIEE Conference
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    • 2003.11b
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    • pp.271-274
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    • 2003
  • This paper presents a Built-in Current Sensor that detect defects in CMOS integrated circuits using the current testing technique. This scheme employs a cross-coupled connected PMOS transistors, it is used as a current comparator. Our proposed scheme is a negligible impart on the performance of the circuit undo. test (CUT). In addition, in the normal mode of the CUT not dissipation extra power, high speed detection time and applicable deep submicron process. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects. The entire area of the test chip is $116{\times}65{\mu}m^2$. The BICS occupies only $41{\times}17{\mu}m^2$ of area in the test chip. The area overhead of a BICS versus the entire chip is about 9.2%. The chip was fabricated with Hynix $0.35{\mu}m$ 2-poly 4-metal N-well CMOS technology.

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CMOS Temperature Sensor with Ring Oscillator for Mobile DRAM Self-refresh Control (링 오실레이터를 가진 CMOS 온도 센서)

  • Kim, Chan-kyung;Lee, Jae-Goo;Kong, Bai-Sun;Jun, Young-Hyun
    • Proceedings of the IEEK Conference
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    • 2006.06a
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    • pp.485-486
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    • 2006
  • This paper proposes a novel low-cost CMOS temperature sensor for controlling the self-refresh period of a mobile DRAM. In this temperature sensor, ring oscillators composed of cascaded inverter stages are used to obtain the temperature of the chip. This method is highly area-efficient, simple and easy for IC implementation as compared to traditional temperature sensors based on analog bandgap reference circuits. The proposed CMOS temperature sensor was fabricated with 80 nm 3-metal DRAM process. It occupies a silicon area of only about less than $0.02\;mm^2$ at $10^{\circ}C$ resolution with under 5uW power consumption at 1 sample/s processing rate. This area is about 33% of conventional temperature sensor in mobile DRAM.

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Fabrication of Gallium Phosphide Tapered Nanostructures on Selective Surfaces

  • Song, Young Min;Park, Hyun Gi
    • Applied Science and Convergence Technology
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    • v.23 no.5
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    • pp.284-288
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    • 2014
  • We present tapered nanostructures fabricated on a selective area of gallium phosphide substrates for advanced optoelectronic device applications. A lithography-free fabrication process was accomplished by dry etching of metal nanoparticles. Thermal dewetting of micro-patterned metal thin films provides etch masks for tapered nanostructures. This simple process also allows the formation of plasmonic surfaces with corrugated shapes. Rigorous coupled-wave analysis calculations provide design guidelines for tapered nanostructures on gallium phosphide substrates.

Thle New Design of a Large Area Dye-sensitized Solar Cell with Ag Grid for Improving a Design Characteristics (설계적 특성 개선을 위한 Ag 그리드를 가지는 대면적 염료감응형 태양전지의 새로운 디자인)

  • Choi, Jin-Young;Lee, Im-Geun;Hong, Ji-Tae;Kim, Mi-Jeong;Kim, Whi-Young;Kim, Hee-Je
    • The Transactions of The Korean Institute of Electrical Engineers
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    • v.56 no.1
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    • pp.123-127
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    • 2007
  • Up sizing of dye-sensitized solar cell(DSC) is the important technology to bring about commercialization of DSC. Several studies to obtain a stable large area DSC have been investigated in overseas laboratories, but have been hardly done in our country. In this study, up sizing technology of dye sensitized solar cells(DSCs) was investigated. We investigated low dark current materials for the current collecting grid. From the result, a new DSC module with metal grid was designed, and fabricated. For a new interconnection, both working and counter electrodes are alternately coupled on 10[cm]$\times$7[cm] substrate. We have achieved 68% of fill factor and photoelectric conversion efficiency of around 2.6% as the best results of new designed DSC structure.

Fabrication and Characteristics of the MAGFET (MAGFET의 제작 및 특성)

  • Kim, Si-Hon;Lee, Cheol-Woo;Lee, Jung-Hwan;Nam, Tae-Chul
    • Journal of Sensor Science and Technology
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    • v.7 no.1
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    • pp.1-8
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    • 1998
  • We have simulated the operating characteristics of the magnetotransistor(MAGFET) by the finite element method and suggested the optimum design conditions to get a maximum sensitivity, The magnetotransistor has been fabricated by CMOS standard processing according to the suggested design conditions and investigated its electromagnetic characteristics. The sensitivity of the magnetotransistor depends on the ratio of width(W) to length(L) of active area rather than its size, and has a maximum when W/L = 1. The relative sensitivity of a fabricated magnetotransistor was 2.53 %/T.

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Design and Fabrication of A Dual-band Open-Ended Circular Ring MoNopole Antenna for WLAN Applications (이중 공진을 갖는 WLAN용 끝이 개방된 원형 링 모노폴 안테나의 설계와 제작)

  • Yoon, Joong-Han
    • The Journal of the Korea institute of electronic communication sciences
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    • v.8 no.7
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    • pp.987-994
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    • 2013
  • In this paper, a dual-band open-ended circular ring moNopole antenna for WLAN(Wireless Local Area Networks) applications. The proposed antenna is based on a planar moNopole design, and composed of open-ended one circular ring of radiating patches for dual-band operation. To obtain the optimized parameters, we used the simulator, Ansoft's High Frequency Structure Simulator(HFSS) and found the parameters that effect antenna characteristics. Using the obtained parameters, the proposed antenna is fabricated. The fabricated antenna is measured at the operating frequencies(2.4-2.484 GHz, 5.15-5.825 GHz), and the return loss coefficient, gain, and radiation patterns are determined.

Development of an Ejector System for Operation of Chemical Lasers (II) - Optimal Design of the Second-Throat Type Annular Supersonic Ejector - (화학레이저 구동용 이젝터 시스템 개발 (II) - 이차목 형태의 환형 초음속 이젝터 최적 설계 -)

  • Kim Sehoon;Jin Jungkun;Kwon Sejin
    • Transactions of the Korean Society of Mechanical Engineers B
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    • v.28 no.10
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    • pp.1231-1237
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    • 2004
  • Determination of geometric design parameters of a second-throat type annual supersonic ejector is described. Tested geometric parameters were primary nozzle area ratio, cross-sectional area of second-throat, L/D ratio of second-throat and primary flow injection angle. Varying these four geometric parameters, we build a test matrix made of 81 test conditions, and experimental apparatus was fabricated to accommodate them. For each test condition, the stagnation pressure of primary flow and the static pressure of the secondary flow were measured simultaneously along with their transition to steady operation and finally to unstarting condition. Comparing the performance curve of every case focused on starting pressure, the unstarting pressure and the minimum secondary pressure, we could derive correlations that the parameters have on the performance of the ejector and presented the optimal design method of the ejector. Additional experiments were carried out to find effects of temperature and mass flow rate of the secondary flow.