• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.3
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• pp.205-210
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• 2001

In this paper, a novel compound mode logic based on the advantage of both CMOS logic and pass-transistor logic(PTL) is proposed. From the experimental results, the power-delay products of the compound mode logic is about 22% lower than that of the conventional CMOS logic, when we design a full adder. With the proposed logic, a high performance 32$\times$32-bit multiplier has been fabricated with 0.6um CMOS technology. It is composed of an improved sign select Booth encoder, an efficient data compressor based on the compound mode logic, and a 64-bit conditional sum adder with separated carry generation block. The Proposed 32$\times$32-bit multiplier is composed of 28,732 transistors with an active area of 1.59$\times$1.68 mm2 except for the testing circuits. From the measured results, the multiplication time of the 32$\times$32-bit multiplier is 9.8㎱ at a 3.3V power supply, and it consumes about 186㎽ at 100MHz.

• Journal of IKEEE
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• v.18 no.1
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• pp.172-178
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• 2014

This paper describes the design technique and the method of analog front-end to measure the saturation of hemoglobin with oxygen sensor. To process the $SpO_2$ value from the sensor, the current data from the sensor should be converted into voltage domain. Designed analog front-end usually converts the current data from the sensor into voltage domain data to pass it on analog-to-digital converter called ADC with a different level of gain characteristics. This circuit was fabricated in a $0.11{\mu}m$ CMOS technology and has 4 level of gain properties. The occupied area is $0.174mm^2$.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.322-330
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• 2014

New effective techniques to repair "small" design errors in integrated circuits are presented. As semiconductor chip complexity increases and the design period becomes tight, errors frequently remain in a fabricated chip making revisions required. Full mask revision significantly increases the cost and time-to-market. However, since many "small" errors can be repaired by modifying several connections among the circuit blocks and spare cells, errors can frequently be repaired by revising metal layers. Metal only revision takes significantly less time and involves less cost when compared to full mask revision, since mask revision costs multi-million dollars while metal revision costs tens of thousand dollars. In our research, new techniques are developed to further reduce the number of metal layers to be revised. Specifically, we partition the circuit blocks with higher error probabilities and extend the terminals of the signals crossing the partition boundaries to the preselected metal repair layers. Our partitioning and pin extension to repair layers can significantly improve the repairability by revising only the metal repair layers. Since pin extension may increase delay slightly, this method can be used for non-timing-critical parts of circuits. Experimental results by using academia and industrial circuits show that the revision of the two metal layers can repair many "small" errors at low-cost and with short revision time. On the average, when 11.64% of the spare cell area and 24.72% of the extended pins are added to the original circuits, 83.74% of the single errors (and 72.22% of the double errors) can be corrected by using two metal revision. We also suggest methods to use our repair techniques with normal commercial vender tools.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.9
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• pp.904-911
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• 2011

This paper deals with transmission characteristics of a new dual resonant structure for designing waveguide band-pass filter. The structure which has a pass-band between two adjacent stop-bands in a single body consists of circular ridged aperture and four armed conducting patch. The dual resonant behavior of the structure can be represented by a combination of LC series and parallel resonant circuits. Also these resonant properties can be easily controlled by varying the geometry of the aperture and four armed conducting patch. Actually, the structure is fabricated on the microstrip substrate by use of etching technique so that it is formed an iris type resonator which can be easily put into the transverse plane of the waveguide. We use WR-90 standard waveguide, adapters, and VNA(vector network analyzer) to measure the resonant characteristics of the structure. It is very useful to design and to improve the cutoff skirts characteristics in the waveguide band-pass filter design area.

• Journal of IKEEE
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• v.17 no.3
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• pp.267-274
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• 2013

This paper presents a design of LLC resonant converter IC for LED backlight unit based on PFM/PWM dual-mode feedback. Dual output LLC resonant architecture with a single inductor is proposed, where the master output is controlled by the PFM and slave output is controlled by the PWM. To regulate the master output PFM is used as feedback to control the frequency of the power switch. On the other hand, PWM feedback is used to control the pulse width of the power switch and to regulate the slave output. This chip is fabricated in 0.35um 2P3M BC(Bipolar-CMOS-DMOS) Process and the die area is $2.3mm{\times}2.2mm$. Current consumptions is 26mA from 5V supply.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.10
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• pp.1-6
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• 2008

The holding voltage of the high-voltage MOSFETs in snapback condition is much smaller than the power supply voltage. Such characteristics may cause the latcup-like problems in the Smart Power ICs if these devices are directly used in the ESD (Electrostatic Discharge) power clamp. In this work, a latchup-free design based on the Drain-Extended PMOS (DEPMOS) adopting gate VDD structure is proposed. The operation region of the proposed gate-VDD DEPMOS ESD power clamp is below the onset of the snapback to avoid the danger of latch-up. From the measurement on the devices fabricated using a $0.35\;{\mu}m$ BCD (Bipolar-CMOS-DMOS) Process (60V), it was observed that the proposed ESD power clamp can provide 500% higher ESD robustness per silicon area as compared to the conventional clamps with gate-driven LDMOS (lateral double-diffused MOS).

• Transactions of the Korean Society of Mechanical Engineers B
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• v.35 no.9
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• pp.969-974
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• 2011

A carbon nanotube (CNT) is a cylindrical carbon nanostructure with good transport properties along the tube's axis. As an approach for realizing the practical use of CNTs, CNT networks are fabricated and their applications in many fields are investigated. To fabricate thin CNT-based films, several methods have been proposed and used. Among these methods, the spray coating method is a robust method for fabricating a large area. However, it is difficult to achieve uniformity in the CNT network. To solve this problem, it is necessary to understand the effect of the sprayprocess parameters on the deposition thickness distribution. In this study, a numerical model for predicting the deposition thickness distribution during the spray process was developed. The spatial deposition thickness distributions obtained according to various nozzle paths were analyzed using the developed numerical model.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.830-833
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• 2007

In this paper, we implemented a $17{\times}17b$ binary digital multiplier using radix-4 Booth;s algorithmand proposed an efficient testing methodology for the full-custom design. A two-stage pipeline architecture was applied to achieve higher throughput and 4:2 adders were used for regular layout structure in the Wallace tree partition. Several chips were fabricated using LG Semicon 0.6-um 3-Metal N-well CMOS technology. We did fault simulations efficiently using the proposed test method resulting in the reduction of the number of faulty nodes by 88%. The chip contains 9115 transistors and the core area occupies $1135^*1545$ mm2. The functional tests using ATS-2 tester showed that it can operate with 24 MHz clock at 5.0 V at room temperature.

• Journal of Korean Ophthalmic Optics Society
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• v.7 no.1
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• pp.75-78
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• 2002

Thirty three layer $TiO_2/SiO_2$ coating mirrors with high reflectance through a 620~820nm wavelength range have been designed and fabricated by electron beam evaporation method. Multilayer films were deposited on glass(BK7) and sequentially. The high reflector design is based on alternating high and low refractive index layers. $n_H$ and $n_L$ such that a "stopband"(or area of high reflectivity) is created that is centered around the design wavelength. ${\lambda}_0$. The measured transmittance spectrum with an incident wavelength at an incident angle of $40^{\circ}{\pm}7^{\circ}$ exhibited a reflectance of 99.9% at the wavelength of 620~820nm but high peak transmittance in the wavelength region from 700 to 740nm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.37 no.8
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• pp.24-32
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• 2000

In this paper, we have designed and fabricated a new type power divider to be efficient to a size and electrical performance by folding each quarter-wavelength 70.7 Ω section into a tightly-coupled "meander-line" and inserting a slit. In this type, because of coupling, the electrical phase of quarter -wavelength line and the performance change. For this reason, with the inductive slit and the tuning of quarter-wavelength line length, we have compensated for those. The inductance value of the inserted slit is decided by its width and depth, therefore, we could improve the electrical performance through optimization of inductance. Input and output return losses of the designed power divider were -34.2 dB, -34.3 dB respectively, and isolation was -36.7 dB at 1.75 GHz. Besides, a new design approach reduced occupied substrate area by 3:1 approximately.