• Journal of KIISE:Computer Systems and Theory
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• v.32 no.9
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• pp.483-490
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• 2005

Recently, flash memory is widely used in embedded applications since it has strong points: non-volatility, fast access speed, shock resistance, and low power consumption. However, due to its hardware characteristics, it requires a software layer called FTL(flash translation layer). The main functionality of FTL is to convert logical addresses from the host to physical addresses of flash memory We present a new FTL algorithm called STAFF(State Transition Applied Fast Flash Translation Layer). Compared to the previous FTL algorithms, STAFF shows five times higher performance than basic block mapping scheme and requires less memory. We provide performance results based on our implementation of STAFF and previous FTL algorithms.

• The KIPS Transactions:PartA
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• v.12A no.7 s.97
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• pp.621-626
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• 2005

Recently, flash memory is widely used in various embedded applications since it has many advantages in terms of non-volatility, fast access speed, shock resistance, and low power consumption. However, it requires a software layer called FTL(Flash Translation Layer) due to its hardware characteristics. We present a new FTL algorithm named LSTAFF(Large State Transition Applied Fast flash Translation Layer) which is designed for large block flash memory The presented LSTAFF is adjusted to flash memory with pages which are larger than operating system data sector sizes and we provide performance results based on our implementation of LSTAFF and previous FTL algorithms using a flash simulator.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.3
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• pp.94-100
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• 2008

It is necessary to develop the flash memory system software FTL(Flash Translation Layer) which is used in mobile storage like Compact Flash memory. In this paper, we design the FTL using clustered hash table and two phase software caching method to translate logical address into physical address fastly. The experimental results show that the address translation performance of CFTL is 13.3% higher than that of NFTL and 8% higher than that of AFTL, and the memory usage of CFTL is 75% smaller than that of AFTL.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.1
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• pp.1-13
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• 2009

Flash memory is widely used as a storage medium of mobile devices such as MP3 players, cellular phones and digital cameras due to its tiny size, low power consumption and shock resistant characteristics. Currently, there are many studies to replace HDD with flash memory because of its numerous strong points. To use flash memory as a storage medium, FTL(Flash Translation Layer) is required since flash memory has erase-before-write constraints and sizes of read/write unit and erase unit are different from each other. Recently, new type of flash memory called "large block flash memory" is introduced. The large block flash memory has different physical structure and characteristics from previous flash memory. So existing FTLs are not efficiently operated on large block flash memory. In this paper, we propose an efficient FTL for large block flash memory based on FAST(Fully Associative Sector Translation) scheme and page-level mapping on data blocks.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.4
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• pp.305-311
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• 2005

Flash memory software running on cellular phones and PDAs need to be tested extensively to cope with abrupt power and media faults. For those tests, we designed and implemented a Flash memory emulator with fault injection features. The fault injection tester has provided a helpful framework for designing fault recovery schemes and also for analyzing fault damages to the FTL (Flash Translation Layer) and file system for a Flash memory based system. In this paper, we discuss Plash memory fault types and fault injection features implemented on this Flash memory emulator. We then discuss in detail a design flaw revealed during fault injection tests. Specifically, it was revealed that a scheme that was believed to improve reliability instead, turned out to be harmful. In addition, we discuss post-fault behaviors of the FTL and the file system.

• ETRI Journal
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• v.30 no.6
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• pp.790-798
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• 2008

Recently, NAND flash memory has emerged as a next generation storage device because it has several advantages, such as low power consumption, shock resistance, and so on. However, it is necessary to use a flash translation layer (FTL) to intermediate between NAND flash memory and conventional file systems because of the unique hardware characteristics of flash memory. This paper proposes a new clustered FTL (CFTL) that uses clustered hash tables and a two-level software cache technique. The CFTL can anticipate consecutive addresses from the host because the clustered hash table uses the locality of reference in a large address space. It also adaptively switches logical addresses to physical addresses in the flash memory by using block mapping, page mapping, and a two-level software cache technique. Furthermore, anticipatory I/O management using continuity counters and a prefetch scheme enables fast address translation. Experimental results show that the proposed address translation mechanism for CFTL provides better performance in address translation and memory space usage than the well-known NAND FTL (NFTL) and adaptive FTL (AFTL).

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.15-18
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• 2003

Flash memory becomes more important for its fast access speed, low-power, shock resistance and nonvolatile storage. But its native restrictions that have limited 1ifetime, inability of update in place, different size unit of read/write and erase operations need to managed by FTL(Flash Translation Layer). FTL has to control the wear-leveling, address mapping, bad block management of flash memory. In this paper, we focuses on the fast access to address mapping table and proposed the way of faster valid page search in the flash memory using the VPLT(Valid Page Lookup Table). This method is expected to decrease the frequency of access of flash memory that have an significant effect on performance of read and block-transfer operations. For the validations, we implemented the FTL based on Windows CE platform and obtained an improved result.

• Journal of KIISE:Computing Practices and Letters
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• v.15 no.2
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• pp.77-88
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• 2009

According to the size of NAND flash memory as the storage system of mobile device becomes large, the performance of address translation and life cycle management in FTL (Flash Translation Layer) to interact with file system becomes very important. In this paper, we propose the continuity counters, which represent the number of continuous physical blocks whose logical addresses are consecutive, to reduce the number of address translation. Furthermore we propose the prefetching method which preloads frequently accessed pages into main memory to enhance I/O performance of flash memory. Besides, we use the 2-bit write prediction and asynchronous writing method to predict addresses repeatedly referenced from host and prevent from writing overhead. The experiments show that the proposed method improves the I/O performance and extends the life cycle of flash memory. As a result, proposed CFTL (Clustered Flash Translation Layer)'s performance of address translation is faster 20% than conventional FTLs. Furthermore, CFTL is reduced about 50% writing time than that of conventional FTLs.

• International journal of advanced smart convergence
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• v.10 no.1
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• pp.142-150
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• 2021

Open-channel SSD is a new type of Solid-State Disk (SSD) that improves the garbage collection overhead and write amplification due to physical constraints of NAND flash memory by exposing the internal structure of the SSD to the host. However, the host-level Flash Translation Layer (FTL) provided for open-channel SSDs in the current Linux kernel consumes host memory excessively because it use page-level mapping table to translate logical address to physical address. Therefore, in this paper, we implemente a selective mapping table loading scheme that loads only a currently required part of the mapping table to the mapping table cache from SSD instead of entire mapping table. In addition, to increase the hit ratio of the mapping table cache, filesystem information and mapping table access history are utilized for cache replacement policy. The proposed scheme is implemented in the host-level FTL of the Linux kernel and evaluated using open-channel SSD emulator. According to the evaluation results, we can achieve 80% of I/O performance using the only 32% of memory usage compared to the previous host-level FTL.

• Journal of the Korea Society of Computer and Information
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• v.22 no.12
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• pp.9-15
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• 2017

This paper presents an efficient FTL for NAND flash based SSDs. Address translation information of page mapping based FTLs is stored on flash memory pages and address translation cache keeps frequently accessed entries. The proposed FTL of this paper reduces response time by considering both of temporal and spacial localities of page access patterns in translation cache management. The localities of several well-known traces are evaluated and determine the structure of the cache for high hit ratio. A simulation with several well-known traces shows that the presented FTL reduces response time in comparison to previous FTLs and can be used with relatively small size of caches.