• 한국정보과학회논문지:시스템및이론
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• 제31권8호
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• pp.453-464
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• 2004

In order to solve the well-known drawback of reduced flexibility that is associate with ASIC implementations, this paper proposes a novel arithmetic unit over GF(2$^{m}$ ) for field programmable gate arrays (FPGAs) implementations of elliptic curve cryptographic processor. The proposed arithmetic unit is based on the binary extended GCD algorithm and the MSB-first multiplication scheme, and designed as systolic architecture to remove global signals broadcasting. The proposed architecture can perform both division and multiplication in GF(2$^{m}$ ). In other word, when input data come in continuously, it produces division results at a rate of one per m clock cycles after an initial delay of 5m-2 in division mode and multiplication results at a rate of one per m clock cycles after an initial delay of 3m in multiplication mode respectively. Analysis shows that while previously proposed dividers have area complexity of Ο(m$^2$) or Ο(mㆍ(log$_2$$^{m}$ )), the Proposed architecture has area complexity of Ο(m), In addition, the proposed architecture has significantly less computational delay time compared with the divider which has area complexity of Ο(mㆍ(log$_2$$^{m}$ )). FPGA implementation results of the proposed arithmetic unit, in which Altera's EP2A70F1508C-7 was used as the target device, show that it ran at maximum 121MHz and utilized 52% of the chip area in GF(2$^{571}$ ). Therefore, when elliptic curve cryptographic processor is implemented on FPGAs, the proposed arithmetic unit is well suited for both division and multiplication circuit.

• Nuclear Engineering and Technology
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• 제54권7호
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• pp.2444-2452
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• 2022

The field-programmable gate array (FPGA) is gaining popularity in industrial automation such as nuclear power plant instrumentation and control (I&C) systems due to the benefits of having non-existence of operating system, minimum software errors, and minimum common reason failures. Separate functions can be processed individually and in parallel on the same integrated circuit using FPGAs in comparison to the conventional microprocessor-based systems used in any plant operations. The use of FPGAs offers the potential to minimize complexity and the accompanying difficulty of securing regulatory approval, as well as provide superior protection against obsolescence. Wireless sensor networks (WSNs) are a new technology for acquiring and processing plant data wirelessly in which sensor nodes are configured for real-time signal processing, data acquisition, and monitoring. ZigBee (IEEE 802.15.4) is an open worldwide standard for minimum power, low-cost machine-to-machine (M2M), and internet of things (IoT) enabled wireless network communication. It is always a challenge to follow the specific topology when different Zigbee nodes are placed in a large network such as a plant. The research article focuses on the hardware chip design of different topological structures supported by ZigBee that can be used for monitoring and controlling the different operations of the plant and evaluates the performance in Vitex-5 FPGA hardware. The research work presents a strategy for configuring FPGA with ZigBee sensor nodes when communicating in a large area such as an industrial plant for real-time monitoring.

• 한국정보통신학회논문지
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• 제10권7호
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• pp.1259-1265
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• 2006

본 논문에서는 고속 FPGA 설계를 위한 논리 수준의 조합회로 합성 알고리듬을 제안한다. 제안된 알고리듬은 회로의 지연시간을 줄이기 위해 critical path를 분할한다. 그리고 분할된 회로를 동시에 수행하는 구조를 갖는 회로를 생성한다. 본 커널 선택 알고리듬은 SUN UNIX 환경에서 C 언어로 구현되었다. 제안된 커널 선택 알고리듬은 기존의 FlowMap 지연시간 최적화 알고리듬과 결과를 비교하였다. 제안된 지연시간 최적화 알고리듬이 기존 알고리듬 에 비해 지연시간이 평균 33.3 % 감소된 회로를 생성함을 보였다.

• 제어로봇시스템학회논문지
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• 제8권12호
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• pp.1036-1040
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• 2002

To process data of digital linescan camera, the frame grabber is essential to handle the data in low-level and in high speed more than 30 MHz stably. Traditional approaches to the development of hardware in vision system for the special purpose are mai y based on PC system, and are expensive and gigantic. Therefore, there are many difficulties in applying those in the field. So we investigate, in this paper, the implementation of FPGA for real-time processing of digital linescan camera. The system is not based on PC, but electronic device such as micropncessor. So it is expected that the use of FPGAs for low-level processing represents a fast, stable and inexpensive system. The experiments are carried out on the web guiding system in order to show the efficiency of the new image processor.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2004년도 학술대회 논문집 정보 및 제어부문
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• pp.129-131
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• 2004

Elliptic Curve Cryptography (ECC) coprocessors support massive scalar multiplications of a point. We research the design for multi-segment multipliers in fixed-size ECC coprocessors using the multi-segment Karatsuba algorithm on GF($2^m$). ECC coprocessors of the proposed multiplier is verified on the SoC-design verification kit which embeds ALTERA EXCALIBUR FPGAs. As a result of our experiment, the multi-segment Karatsuba multiplier, which has more efficient performance about twice times than the traditional multi-segment multiplier, can be implemented as adding few H/W resources. Therefore the multi-segment Karatsuba multiplier which satisfies performance for the cryptographic algorithm, is adequate for a low cost embedded system, and is implemented in the minimum area.

• 한국항공우주학회지
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• 제31권4호
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• pp.105-111
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• 2003

과학위성 1호 탑재 컴퓨터의 인증모델 개발이 완료되었다. 과학위성 1호 탑재 컴퓨터는 우리별 3호에 비하여 FPGA를 사용함으로써 크기 및 무게의 소형화를 추구하였고, 네트워크 제어기를 내장함으로써 고속으로 위성 네트워크에 접속할 수 있도록 하였다. 또한 우주환경에서 직면하게 되는 SEU(Single Event Upset)에 대한 강인성이 증대되었고, 내고장성도 증대되었다. 개발된 탑재 컴퓨터는 환경시험에서 모든 기능이 정상 동작함을 확인하였다.

• 제어로봇시스템학회논문지
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• 제6권2호
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• pp.228-233
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• 2000

It is common to apply the technology of FPGA (Fie이 Programmable Gate Array) which is one of the design methods for ASIC(Application Specific IC)to the active components used in the data processing at the digital system of satellite aircraft missile etc for compact lightness and integration of Printed Circuit Board (PCB) In carrying out the digital data processing the FPGAs are designed for the various functions of the Process Control Interrupt Control Clock Generation Error Detection and Correction (EDAC) as the individual module. In this paper an FPGA chip for Single Error Correction and Double Error Detection (SEC-DED) for EDAC is designed and simulated by using a VLSI design software LODECAP.

• 한국통신학회논문지
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• 제22권6호
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• pp.1185-1194
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• 1997

It is necessary to control the frame memory to capture, edit and display images. This paper presents the free-scale image capture processor size of which is user-defined, compared to the conventional image capture processor size of which is fixed 1/2, 1/4 and full size. User-defined scale data is fed into this system, which generates the gating pulses and gates the inputted image data. This system also controls the 4M DRAM instead of frame meamory. And stored gated image data are displayed on the TV monitor. We designed the scalable image capture parts and DRAM controller with ACTEL FPGAs, simulated the circuits with Viewlogic and fusing ACTEL A1020B chips. We confirmed the whole operation with beadboard which composed of "Philips TV Chipset" and designed FPGA chips.PGA chips.

• 한국통신학회논문지
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• 제22권11호
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• pp.2365-2374
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• 1997

This paper describes two algorithms for technology mapping of multiple output functions into interesting and pupular FPGAs(Field Programmable Gate Array) that use look-yp table memories. For improvement of technology mapping for FPGA, we use the functional decompoition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karpalgorithm extended for multiple output functions. The other is the efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental resutls show sigificant reduction in the number of CLBs and nets.

• 전자공학회논문지A
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• 제33A권10호
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• pp.177-185
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• 1996

This paper describes several algorithms for technolgoy mapping of logic functions into interesting and popular FPGAs that use look-up table memories. In order to improved the technology mapping for FPGA, some existing multi-level logic synthesis, decomposition reduction and packing techniques are analyzed and compared. And then new algorithms such as merging fanin, unified reduction and multiple disjoint decomposition which are used for combinational logic design, are proposed. The cost function is used to minimize the number of CLBs and edges of the network. The cost is a linear combination of each weight that is given by user. Finally we compare our new algorithm with previous logic design technique. In an experimental comparison our algorithm requires 10% fewer CLB and nets than SIS-pga.