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Delay optimization algorithm on FPGAs  

Hur Chang-Wu (목원대학교 정보전자영상공학부)
Kim Nam-Woo ((주)휴인스)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.10, no.7, 2006 , pp. 1259-1265 More about this Journal
Abstract
In this paper, we propose a combined synthetic algorithm of the logic level for high speed FPGA design. The algorithm divides critical path to reduce delay time and generates a circuit which the divided circuits execute simultaneously. This kernel selection algorithm is made by C-langage of SUN UNIX. We compare this with the existing FlowMap algorithm. This proposed algorithm shows result on 33.3% reduction of delay time by comparison with the existing algorithm.
Keywords
FAGA;
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  • Reference
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