• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.165-175
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• 2010

This paper presents a fine-grain supply-voltage-control scheme for low-power FPGAs. The proposed supply-voltage-control scheme detects the critical path in real time with small overheads by exploiting features of asynchronous architectures. In an FPGA based on the proposed supply-voltage-control scheme, logic blocks on the sub-critical path are autonomously switched to a lower supply voltage to reduce the power consumption without system performance degradation. Moreover, in order to reduce the overheads of level shifters used at the power domain interface, a look-up-table without level shifters is employed. Because of the small overheads of the proposed supply-voltage-control scheme and the power domain interface, the granularity size of the power domain in the proposed FPGA is as fine as a single four-input logic block. The proposed FPGA is fabricated using the e-Shuttle 65 nm CMOS process. Correct operation of the proposed FPGA on the test chip is confirmed.

• International Journal of Aeronautical and Space Sciences
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• v.18 no.4
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• pp.675-687
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• 2017

In the aerospace industry, we have produced various models according to operational conditions and the environment after development of the base model is completed. Therefore, when design change is necessary, there are modification and updating costs of the circuit whenever environment variables change. For these reasons, recently, in various fields, system designs that can flexibly respond to changing environmental conditions using field programmable gate arrays (FPGAs) are attracting attention, and the rapidly changing aerospace industry also uses FPGAs to organize the system environment. In this paper, we design the controller area network (CAN) intellectual property (IP) protocol used instead of the avionics protocol that includes ARINC-429 and MIL-STD-1553, which are not suitable for small unmanned aerial vehicle (UAV) systems at the register transistor logic (RTL) level, which does not depend on the FPGA vender, and we verify the performance. Consequentially, a Spartan 6 FPGA model-based system on chip (SoC) including an embedded system is constructed by using the designed CAN communications IP and Xilinx Microblaze, and the configured SoC only recorded an average 32% logic element usage rate in the Spartan 6 FPGA model.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.11
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• pp.40-49
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• 2009

HAO is a ORB engine to support the logic-based CORBA development environments in FPGA. In this papers, in order to support the logic component developments with HAO, we proposes the translation rule from IDL to VHDL, and the generation of skeleton logic code following the rule. It enables to guarantee the interoperability between the components in distributed multi processor environments includes the general purpose processor and FPGAs, and to improve the performance through the usage of logic-circuit.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.97-102
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• 2007

This paper presents our implemented, synthesized and tested on demand and partial reconfiguration approaches for FIR filters using Xilinx Virtex FPGAs. Our scope is implementation of a low-power, area-efficient autonomously reconfigurable digital signal processing architecture that is tailored for the realization of arbitrary response FIR filters on Xilinx Virtex4 FPGAs. The implementation of design addresses area efficiency and flexibility allowing dynamically inserting and/or removing the partial modules to implement the partial reconfigurable FIR filters with various taps. This partial reconfigurable FIR filter design shows the configuration time improvement, good area efficiency and flexibility by using the dynamic partial reconfiguration method.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.6 no.9
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• pp.2388-2404
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• 2012

Cryptographic hash functions are widely used in many information security applications like digital signatures, message authentication codes (MACs), and other forms of authentication. In response to recent advances in cryptanalysis of commonly used hash algorithms, National Institute of Standards and Technology (NIST) announced a publicly open competition for selection of new standard Secure Hash Algorithm called SHA-3. One important aspect of this competition is evaluation of hardware performances of the candidates. In this work we present efficient hardware implementations of SHA-3 finalists: JH, Keccak and Skein. We propose high speed architectures using Look-Up Table (LUT) resources on FPGAs, to minimize chip area and to reduce critical path lengths. This approach allows us to design data paths of SHA-3 finalists with minimum resources and higher clock frequencies. We implemented and investigated the performance of these candidates on modern and latest FPGA devices from Xilinx. This work serves as performance investigation of leading SHA-3 finalists on most up-to-date FPGAs.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1B
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• pp.47-55
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• 2009

In recent network intrusion detection systems, regular expressions are used to represent malicious packets. In order to process incoming packets through high speed networks in real time, we should perform hardware-based pattern matching using the configurable device such as FPGAs. However, operating speed of FPGAs is slower than giga-bit speed network and so, multi-byte processing per clock cycle may be needed. In this paper, we propose a hardware architecture of multi-byte based regular expression pattern matching and implement the pattern matching circuit generator. The throughput improvements in four-byte based pattern matching circuit synthesized in FPGA for several Snort rules are $2.62{\sim}3.4$ times.

• Nuclear Engineering and Technology
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• v.48 no.5
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• pp.1192-1205
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• 2016

Field programmable gate array (FPGA)-based systems are thought to be a practical option to replace certain obsolete instrumentation and control systems in nuclear power plants. An FPGA is a type of integrated circuit, which is programmed after being manufactured. FPGAs have some advantages over other electronic technologies, such as analog circuits, microprocessors, and Programmable Logic Controllers (PLCs), for nuclear instrumentation and control, and safety system applications. However, safety-related issues for FPGA-based systems remain to be verified. Owing to this, modeling FPGA-based systems for safety assessment has now become an important point of research. One potential methodology is the dynamic flowgraph methodology (DFM). It has been used for modeling software/hardware interactions in modern control systems. In this paper, FPGA logic was analyzed using DFM. Four aspects of FPGAs are investigated: the "IEEE 1164 standard," registers (D flip-flops), configurable logic blocks, and an FPGA-based signal compensator. The ModelSim simulations confirmed that DFM was able to accurately model those four FPGA properties, proving that DFM has the potential to be used in the modeling of FPGA-based systems. Furthermore, advantages of DFM over traditional reliability analysis methods and FPGA simulators are presented, along with a discussion of potential issues with using DFM for FPGA-based system modeling.

• The Transactions of the Korea Information Processing Society
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• v.3 no.3
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• pp.564-571
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• 1996

The logic synthesis systems for table look up(TLU) type field programmable e gate arrays(FPGAs) have so farstudied mostly the combinational logic problem m. This paper presents for mapping a sequential circuit onto a popular table look up architecture, theXilinx 3090 architecture. In thefirst for solving this problem, combinational and sequential elements which have 6 or7 input combinational and sequential elements which haveless thanor equal to 5 inputs. We heavily use the combinational synthesis techniques tosolve the sequential synthesis problem. Our syntheisis approach is very simple, but its results are reasonable. We compare seveal benchmark Examples with sis-pga(map_together and map_separate) synthesis system and the experimental results show that our synthesis system is 17% betterthan sis-pga sequential synthesis system for TLU PGAs.

• The Transactions of the Korea Information Processing Society
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• v.4 no.11
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• pp.2923-2930
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• 1997

This paper describes two algorithms for technology mapping of multiple output functions into interesting and popular FPGAs (Field Programmable Gate Arrays) that lise look-up table memories. For improvement of technology mapping for FPGA, we use the functional decomposition method for multiple output functions. Two algorithms are proposed. The one is the Roth-Karp algorithm extended for multiple output functions. The other is the novel and efficient algorithm which looks for common decomposition functions through the decomposition procedure. The cost function is used to minimize the number of CLBs and nets and to improve performance of the network. Finally we compare our new algorithm with previous logic design technique. Experimental results show significant reduction in the number of CLBs and nets.

• Proceedings of the KIEE Conference
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• 2003.11c
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• pp.563-566
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• 2003

We have designed the power control unit which belongs to the power cabinet and controls the power supplied to Control Rod Drive Mechanism(CRDM) as a digital system based on Digital Signal Processor(DSP). The power control unit dualized as the form of Master/Slave has had its increased reality. The Central Process Unit(CPU) board of a power control unit possesses two Digital Signal Processors(DSPs) of the control DSP for performing the tasks of power control and system monitoring and the communication of the Control DSP and the Communication DSP. To accomplish the functions requested in the power control unit effectively, we have installed Field Programmable Gate Arrays(FPGAS) on the CPU board and have FPGAs perform the memory mapping, the generation of each chip selection signal, the giving and receiving of the signals between the power controllers dualized, the fault detection and the generation of the firing signals.