• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.1
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• pp.100-106
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• 2017

In this paper, we propose a parallel optimization method of Aho-Corasick (AC) algorithm and Parallel Failureless Aho-Corasick (PFAC) algorithm using Open Computing Language (OpenCL) on Field Programmable Gate Array (FPGA). The low throughput of string matching engine causes the performance degradation of network process. Recently, many researchers have studied the string matching engine using parallel computing. FPGA's vendors offer a parallel computing platform using OpenCL. In this paper, we apply the AC and PFAC algorithm on DE1-SoC board with Cyclone V FPGA, where the optimization that considers FPGA architecture is performed. Experiments are performed considering global id, local id, local memory, and loop unrolling optimizations using PFAC algorithm. The performance improvement using loop unrolling is 129 times greater than AC algorithm that not adopt loop unrolling. The performance improvements using loop unrolling are 1.1, 0.2, and 1.5 times greater than those using global id, local id, and local memory optimizations mentioned above.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.1B
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• pp.47-55
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• 2009

In recent network intrusion detection systems, regular expressions are used to represent malicious packets. In order to process incoming packets through high speed networks in real time, we should perform hardware-based pattern matching using the configurable device such as FPGAs. However, operating speed of FPGAs is slower than giga-bit speed network and so, multi-byte processing per clock cycle may be needed. In this paper, we propose a hardware architecture of multi-byte based regular expression pattern matching and implement the pattern matching circuit generator. The throughput improvements in four-byte based pattern matching circuit synthesized in FPGA for several Snort rules are $2.62{\sim}3.4$ times.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.5
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• pp.465-472
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• 2016

This study materialized an FPGA-based system to extract PCB patterns. The Printed Circuit Boards that are produced these days are becoming more detailed and complex. Therefore, the importance of a vision system to extract defects of detailed patterns is increasing. This study produced an FPGA-based system that has high speed handling for vision automation of the PCB production process. A vision library that is used to extract defect patterns was also materialized in IPs to optimize the system. The IPs materialized are Camera Link IP, pattern matching IP, VGA IP, edge extraction IP, and memory IP.

• Journal of the Korea Society of Computer and Information
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• v.17 no.4
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• pp.11-18
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• 2012

Deep packet inspection which perform pattern matching to search for malicious patterns in the packet is most computationally intensive task. Hardware-based pattern matching is required for real-time packet inspection in high-speed network. In this paper, we have designed and implemented network intrusion detection hardware as a Microblaze-based SoC using Virtex-6 FPGA, which capture the network input packet, perform hardware-based pattern matching for patterns in the Snort rule, and provide the matching result to the software. We verify the operation of the implemented system using traffic generator and real network traffic. The implemented hardware can be used in network intrusion detection system operated in wire-speed.

• Journal of Broadcast Engineering
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• v.18 no.5
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• pp.669-679
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• 2013

This paper proposed a new VLSI (Very Large Scale Integrated Circuit) architecture for stereo matching in real time. We minimized the amount of calculation and the number of memory accesses through analyzing calculation of stereo matching. From this, we proposed a new stereo matching calculating cell and a new hardware architecture by expanding it in parallel, which concurrently calculates cost function for all pixels in a search range. After expanding it, we proposed a new hardware architecture to calculate cost function for 2-dimensional region. The implemented hardware can be operated with minimum 250Mhz clock frequence in FPGA (Field Programmable Gate Array) environment, and has the performance of 805fps in case of the search range of 64 pixels and the image size of $640{\times}480$.

• Journal of KIISE
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• v.44 no.9
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• pp.932-945
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• 2017

In this paper, a new hardware and software architecture for a stereo vision processing system including rectification, disparity estimation, and visualization was developed. The developed method, named LArge scale stereo matching method using Support Point Interpolation (LASPI), shows excellence in real-time processing for obtaining dense disparity maps from high quality image regions that contain high density support points. In the real-time processing of high definition (HD) images, LASPI does not degrade the quality level of disparity maps compared to existing stereo-matching methods such as Efficient LArge-scale Stereo matching (ELAS). LASPI has been designed to meet a high frame-rate, accurate distance resolution performance, and a low resource usage even in a limited resource environment. These characteristics enable LASPI to be deployed to safety-critical applications such as an obstacle recognition system and distance detection system for autonomous vehicles. A Field Programmable Gate Array (FPGA) for the LASPI algorithm has been implemented in order to support parallel processing and 4-stage pipelining. From various experiments, it was verified that the developed FPGA system (Xilinx Virtex-7 FPGA, 148.5MHz Clock) is capable of processing 30 HD ($1280{\times}720pixels$) frames per second in real-time while it generates disparity maps that are applicable to real vehicles.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.9
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• pp.2071-2077
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• 2010

Interface modules design between image sensor and external components are designed by FPGA (Field Programmable Gate Array) in this paper. Generally speaking, to satisfy synchronization for the poor quality data in image, SRAM is needed. To receive synchronization signal and image signal data with pixel dimension, the proposed interface logic technique is implemented. From the proposed technique, we can obtain more clear screen by implementing with pixel dimension. Operating frequency of image sensor and that of TFT-LCD are 50MHz and 6.5MHz, respectively. Most of control logic functions are embedded in FPGA. The designed logic gate counter has 33,216 and is designed by Quartus II.

• The KIPS Transactions:PartC
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• v.16C no.5
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• pp.583-588
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• 2009

Network intrusion detection system (NIDS) monitors all incoming packets in the network and detects packets that are malicious to internal system. The NIDS should also have ability to update detection rules because new attack patterns are unpredictable. Incorporating FPGAs into the NIDS is one of the best solutions that can provide both high performance and high flexibility comparing with other approaches such as software solutions. In this paper we propose and design a novel approach, prefix sharing parallel pattern matcher, that can not only minimize additional resources but also maximize the processing performance. Experimental results showed that the throughput for 16-bit input is twice larger than for 8-bit input but the used LEs/Char in FPGA increases only 1.07 times.

• Journal of the Korea Society of Computer and Information
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• v.11 no.2 s.40
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• pp.159-167
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• 2006

Lipreading has been suggested as one of the methods to improve the performance of speech recognition in noisy environment. However, existing methods are developed and implemented only in software. This paper suggests a hardware design for real-time lipreading. For real-time processing and feasible implementation, we decompose the lipreading system into three parts; image acquisition module, feature vector extraction module, and recognition module. Image acquisition module capture input image by using CMOS image sensor. The feature vector extraction module extracts feature vector from the input image by using parallel block matching algorithm. The parallel block matching algorithm is coded and simulated for FPGA circuit. Recognition module uses HMM based recognition algorithm. The recognition algorithm is coded and simulated by using DSP chip. The simulation results show that a real-time lipreading system can be implemented in hardware.

• The Journal of the Korea institute of electronic communication sciences
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• v.13 no.2
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• pp.435-442
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• 2018

This study implemented an FPGA-based system to extract PCB defect patterns. The FPGA-based system can perform pattern matching at high speed for vision automation. An image processing library that is used to extract defect patterns was also implemented in IPs to optimize the system. The IPs implemented are Camera Link IP, Histogram IP, VGA IP, Horizontal Projection IP and Vertical Projection IP. In terms of hardware, the FPGA chip from the Vertex-5 of Xilinx was used to receive and handle images that are sent from a digital camera. This system uses MicroBlaze CPU. The image results are sent to PC and displayed on a 7inch TFT-LCD and monitor.