• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.66-76
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• 2009

The motion estimation in video encoding system occupies the biggest part. So, we require the motion estimator with efficient structure for real-time operation. And for motion estimator's implementation, it is desired to design hardware module of an exclusive use that perform the encoding process at high speed. This paper proposes motion estimation detection block(MED), 41 SADs(Sum of Absolute Difference) calculation block, minimum SAD calculation and motion vector generation block based on parallel processing. The parallel processing can reduce effectively the amount of the operation. The minimum SAD calculation and MED block uses the pre-computation technique for reducing switching activity of the input signal. It results in high-speed operation. The MED and 41 SADs calculation blocks are composed of adder tree which causes the problem of critical path. So, the structure of adder tree has changed the most commonly used ripple carry adder(RCA) with carry skip adder(CSA). It enables adder tree to operate at high speed. In addition, as we enabled to easily control key variables such as control signal of search range from the outside, the efficiency of hardware structure increased. Simulation and FPGA verification results show that the delay of MED block generating the critical path at the motion estimator is reduced about 19.89% than the conventional strukcture.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.27 no.3
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• pp.326-329
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• 2016

UAVs(Unmanned Aerial Vehicle) can be used in variant fields fornot only combat, but also recon, observation and exploration. Moreover, UAVs capacity can be expanded to impossible missions for existing surveillance system such as SAR(Synthetic Aperture Radar) technology that collecting images from all weather conditions. In recent days, with development of highly efficient IC and lightened system technology, there are significant increase of researches and demands to make SAR sensor as a payload of UAV. Therefore, this paper contains development process and results of small signal generator and RF device as a core module of SAR system based on the digital device of DDS.

• Journal of Information Technology Services
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• v.8 no.2
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• pp.147-156
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• 2009

As the result of the rapid development of IT technology, an on-line diagnostic system using the field bus communication network coupled with a smart sensor module will be widely used at the nuclear power plant in the near future. The smart sensor system is very useful for the prompt understanding of abnormal state of the key equipments installed in the nuclear power plant. In this paper, it is assumed that a smart sensor system based on the fieldbus communication network for the surveillance and diagnostics of safety-critical equipments will be installed in the harsh-environment of the nuclear power plant. It means that the key components of fieldbus communication system including microprocessor, FPGA, and ASIC devices, are to be installed in the RPV (reactor pressure vessel) and the RCS (reactor coolant system) area, which is the area of a high dose-rate gamma irradiation fields. Gamma radiation constraints for the DBA (design basis accident) qualification of the RTD sensor installed in the harsh environment of nuclear power plant, are typically on the order of 4 kGy/h. In order to use a field bus communication network as an ad-hoc diagnostics sensor network in the vicinity of the RCS pump area of the nuclear power plant, the robust survivability of IT-based micro-electronic components in such intense gamma-radiation fields therefore should be verified. An intelligent CCD camera system, which are composed of advanced micro-electronics devices based on IT technology, have been gamma irradiated at the dose rate of about 4.2kGy/h during an hour UP to a total dose of 4kGy. The degradation performance of the gamma irradiated CCD camera system is explained.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.322-332
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• 2011

In this paper, we introduce the 1st performance evaluation of VLBI Correlation Subsystem (VCS) main product, which is core system of Korea-Japan Joint VLBI Correlator (KJJVC). The main goal of the 1st performance evaluation of VCS main product is that the perfection of overall system will be enhanced after checking the unsolved part by performing the experiments towards various test items at the manufacturer before installation of field. The functional test was performed by including the overflow problem occurred in the FFT re-quantization module due to the insufficient of effective bit at the VCS trial product in this performance test of VCS main product. Through the performance test for VCS main product in the factory, the problem such as FFT re-quantization discovered at performance test of VCS trial product in 2008 was clearly solved and the important functions such as delay tracking, daly compensation, and frequency bining were added in this VCS main product. We also confirmed that the predicted correlation results (fringe) was obtained in the correlation test by using real astronomical observed data(wideband/narrow band).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.129-136
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• 2005

A multiplier generator, VPM_Gen (Variable-Precision Multiplier Generator), which generates Verilog-HDL models of multiplier cores with user-defined bit-width specification, is described. The bit-widths of operands are parameterized in the range of $8-bit{\sim}32-bit$ with 1-bit step, and the product from multiplier core can be truncated in the range of $8-bit{\sim}64-bit$ with 2-bit step, resulting that the VPM_Gen can generate 3,455 multiplier cores. In the case of truncating multiplier output, by eliminating the circuits corresponding to the truncation part, the gate counts and power dissipation can be reduced by about 40% and 30%, respectively, compared with full-precision multiplier. As a result, an area-efficient and low-power multiplier core can be obtained. To minimize truncation error, an adaptive error-compensation method considering the number of truncation bits is employed. The multiplier cores generated by VPM_Gen have been verified using Xilinx FFGA board and logic analyzer.

• Journal of the Korea Institute of Military Science and Technology
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• v.17 no.1
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• pp.90-95
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• 2014

The system design and the system performance analysis of 3D imaging laser radar system for the mapping purpose is addressed in this article. For the mapping, a push-bloom scanning method is utilized. The pulsed fiber laser with high pulse energy and high pulse repetition rate is used for the light source of laser radar system. The high sensitive linear mode InGaAs avalanche photo-diode is used for the laser receiver module. The time-of-flight of laser pulse from the laser to the receiver is calculated by using high speed FPGA based signal processing board. To reduce the walk error of laser pulse regardless of the intensity differences between pulses, the time of flight is measured from peak to peak of laser pulses. To get 3D image with a single pixel detector, Risley scanner which stirs the laser beam in an ellipsoidal pattern is used. The system laser energy budget characteristics is modeled using LADAR equation, from which the system performances such as the pulse detection probability, false alarm and etc. are analyzed and predicted. The test results of the system performances are acquired and compared with the predicted system performance. According to test results, all the system requirements are satisfied. The 3D image which was acquired by using the laser radar system is also presented in this article.

• The KIPS Transactions:PartA
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• v.9A no.4
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• pp.459-466
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• 2002

Modern embedded system employs a hybrid architecture which contains a general micro processor and reconfigurable devices such as FPGAS to retain flexibility and to meet timing constraints. It is a hard and important problem for embedded system designers to explore and find a right system configuration, which is known as design space exploration (DSE). With DES, it is possible to predict a final system configuration during the design phase before physical implementation. In this paper, we implement a timing analysis simulator for a DSE on a hybrid embedded system. The simulator, integrating exiting timing analysis tools for hardware and software, is designed by extending Y-chart approach, which allows quantitative performance analysis by varying design parameters. This timing analysis simulator is expected to reduce design time and costs and be used as a core module of a DSE for a hybrid embedded system.

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.83-94
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• 2006

This paper describes ATM cell encipherment method using Rijndael Algorithm adopted as an AES(Advanced Encryption Standard) by NIST in 2001. ISO 9160 describes the requirement of physical layer data processing in encryption/decryption. For the description of ATM cell encipherment method, we implemented ATM data encipherment equipment which satisfies the requirements of ISO 9160, and verified the encipherment/decipherment processing at ATM STM-1 rate(155.52Mbps). The DES algorithm can process data in the block size of 64 bits and its key length is 64 bits, but the Rijndael algorithm can process data in the block size of 128 bits and the key length of 128, 192, or 256 bits selectively. So it is more flexible in high bit rate data processing and stronger in encription strength than DES. For tile real time encryption of high bit rate data stream. Rijndael algorithm was implemented in FPGA in this experiment. The boundary of serial UNI cell was detected by the CRC method, and in the case of user data cell the payload of 48 octets (384 bits) is converted in parallel and transferred to 3 Rijndael encipherment module in the block size of 128 bits individually. After completion of encryption, the header stored in buffer is attached to the enciphered payload and retransmitted in the format of cell. At the receiving end, the boundary of ceil is detected by the CRC method and the payload type is decided. n the payload type is the user data cell, the payload of the cell is transferred to the 3-Rijndael decryption module in the block sire of 128 bits for decryption of data. And in the case of maintenance cell, the payload is extracted without decryption processing.