• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.26 no.4
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• pp.424-434
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• 2015

Adaptive beamforming algorithms have been widely used to remove interference and jamming in the phased array radar system. Advances in the field programmable gate array(FPGA) technology now make possible the real time processing of adaptive beamforming (ABF) algorithm. In this paper, the FPGA based real-time implementation method of adaptive beamforming system(beamformer) in the pre-processor module for active electronically scanned array(AESA) radar is proposed. A compact FPGA-based adaptive beamformer is developed using commercial off the shelf(COTS) FPGA board with communication via OpenVPX(Virtual Path Cross-connect) backplane. This beamformer comprises a number of high speed complex processing including QR decomposition & back substitution for matrix inversion and complex vector/matrix calculations. The implemented result shows that the adaptive beamforming patterns through FPGA correspond with results of simulation through Matlab. And also confirms the possibility of application in AESA radar due to the real time processing of ABF algorithm through FPGA.

• Proceedings of the Korea Institutes of Information Security and Cryptology Conference
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• 2001.11a
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• pp.403-406
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• 2001

본 논문에서는 차세대 표준 알고리즘(AES: Advanced Encryption Standard)인 Rijndael 알고리즘의 고속화를 FPGA로 구현하였다. Rijndael 알고리즘은 미국 상무부 기술 표준국(NIST)에 의해 2000년 10월에 차세대 표준으로 선정된 블록 암호 알고리즘이다. FPGA(Field Programmable Gate Array)는 아키텍쳐의 유연성이 가장 큰 장점이며, 근래에는 성능면에서도 ASIC에 비견될 정도로 향상되었다. 본 논문에서는 128비트 키 길이와 블록 길이를 가지는 암호화(Encryption)블럭을 Xilinx VirtexE XCV812E-8-BG560 FPGA에 구현하였으며 약 15Gbits/sec의 성능(throughput)을 가진다. 이는 현재까지 발표된 FPGA Rijndael 알고리즘의 구현 사례 중 가장 빠른 방법 중의 하나이다.

• Proceedings of the IEEK Conference
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• 2001.06d
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• pp.49-52
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• 2001

This paper presents a FPGA Implementation of wavelet-based CODEC, which can compress 2-dimensional image. For real-time processing, a scheduling method of input image data is proposed and a new structure of MAC(multiplier-accumulator) is proposed for wavelet transforms. Also this study proposes global pipelining structure of wavelet CODEC and efficient buffering method at interfaces between each module with different clock frequency.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.2
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• pp.57-64
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• 2009

This paper presents the hardware implementation of the pyramidal KLT(Kanade-Lucas-Tomasi) feature tracker. Because of its high computational complexity, it is not easy to implement a real-time KLT feature tracker using general-purpose processors. A hardware implementation of the pyramidal KLT feature tracker using FPGA(Field Programmable Gate Array) is described in this paper with emphasis on 1) adaptive adjustment of threshold in feature extraction under diverse lighting conditions, and 2) modification of the tracking algorithm to accomodate parallel processing and to overcome memory constraints such as capacity and bandwidth limitation. The effectiveness of the implementation was evaluated over ones produced by its software implementation. The throughput of the FPGA-based tracker was 30 frames/sec for video images with size of $720{\times}480$.

• Journal of Communications and Networks
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• v.1 no.3
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• pp.201-212
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• 1999

This paper studies the rapid design and implementation of the medium access control(MAC) and related interface circuits for 802.11 wireless LANs based on the field programmed gate ar-ray(FPGA) technology. Our design is thus aimed to support both the distributed coordination function (DCF) and the point coordination function(PCF) with the aid of FPGA technology. Further-more, in an infrastructure network, some stations may serve as the access points (APs) which may function like a learning bridge. This paper will also discuss how to design for such application. The hardware of the MAC and interface may at least consist of three major parts: wireless transmission and reception processes and in-terface, host(bus) interface, and the interface to the distributed system (optional). Through the increasing popularity of FPGA de-sign, this paper presents how Complex Programmable Logic De-vices(CPLD) can be utilized for speedy design of prototypes. It also demonstrates that there is much room for low-cost hardware prototype design to accelerate the processing speed of the MAC control function and for field testing.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.1028-1031
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• 2003

The implementation of PI controller with the FPGA is for controlling the speed of DC motor in the digital system. FPGA is assigned to 1. Outer speed control loop. The signal from the speed comparison will be in the PI controlling form transfer function of Direct Form I or PI Parallel Form. 2.Inner current control loop. The signal from the current comparison will be converted into switching function in sliding mode condition. Its output will be a controller of DC motor in the next step. The result from using FPGA will be close to the value of simulation in the analog control system. The sampling rate 40 kHz and 16 bit of 2's complement data are defined in this presentation.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.2315-2318
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• 2003

The Wavelet Transform has been applied in mathematics and computer sciences. Numerous studies have proven its advantages in image processing and data compression, and have made it a basic encoding technique in data compression standards like JPEG2000 and MPEG-4. Software implementations of the Discrete Wavelet Transform (DWT) appears to be the performance bottleneck in real-time systems in terms of performance. And hardware implementations are not flexible. Therefore, FPGA implementations of the DWT has been a topic of recent research. The goal of this thesis is to investigate of FPGA implementations of the DWT Processor for image compression applications. The DWT processor design is based on the Lifting Based Wavelet Transform Scheme, which is a fast implementation of the DWT The design uses various techniques. The DWT Processor was simulated and implemented in a FLEX FPGA platform of Altera

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2007.10a
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• pp.363-366
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• 2007

This paper evaluated the performance of circuit for compensate the frequency offset in OFDM using Simulink and designed a System Generator model for FPGA implementation. System Generator Model generated HDL code and RTL schematic. Also, evaluate the performance through Hardware Co-simulation, and investigated the result of timing analysis and resource estimation.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.689-691
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• 2012

In this study, a MDDI protocol packet generation method that is implemented in software is proposed. MDDI protocol is used widely for display device. In this study, MDDI protocol packets are generated by software within micro processor. This method needs minimum hardware configuration. For implementation of this method, we design a hardware platform with a high performance microprocessor and a FPGA. The packets generated by software within microprocessor is converted into LVDS signals, and transmitted by hardware within FPGA.

• Journal of Digital Contents Society
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• v.6 no.3
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• pp.169-174
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• 2005

In this paper we propose efficient design and implementation of JPEG image display board that can display JPEG image on TV. we used NAND Flash Memory to save the compressed JPEG bit stream and video encoder to display the decoded JPEG mage on TV. Also we convert YCbCr to RGB to super impose character on JPEG image. The designed B/D is implemented using FPGA.