• Journal of the Semiconductor & Display Technology
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• v.22 no.4
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• pp.59-65
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• 2023

Edge detection in image processing and computer vision is one of the most fundamental operations. Canny edge detection algorithm has excellent performance and is currently widely used. However, it is difficult to process the algorithm in real-time because the algorithm is complex. In this study, the equations required in the algorithm were simplified to facilitate hardware implementation, and the calculation speed was increased by using a parallel structure. In particular, the size and management of local buffers were selected in consideration of parallel processing and filter size so that data could be processed without bottlenecks. It was designed in verilog and implemented in FPGA to verify operation and performance.

• Proceedings of the Korea Information Processing Society Conference
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• 2007.05a
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• pp.1117-1120
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• 2007

본 논문에서는 개선된 F함수를 이용 하여 국내 표준 128비트 블록 암호화 알고리듬인 SEED 암호 프로세서의 FPGA 구현에 관하여 기술한다. 제안한 SEED 암호 프로세서는 Verilog-HDL를 사용하여 구조적 모델링을 하였으며, Xilinx사의 ISE 9.1i 툴을 이용하여 논리 합성을 수행하였다. 설계 검증은 Modelsim 6.2c 툴을 이용하여 타이밍 시뮬레이션을 수행하였으며, FPGA Prototype 시스템을 사용하여 설계된 하드웨어 동작을 검증하였다.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.46 no.6
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• pp.66-77
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• 2009

In this paper, we propose a CORBA middleware extension which is suitable to SCA based communication environment. The extensions guarantee the components to interconnect others without consideration about its implementation way and enables the developers to easily achieve the performance improvements in comparison to the existing methodology. This extension includes the HAO, the IDL2VHDL compiler, and the improvement of ORBit. The HAO is ORB implemented in logic level and is limited the some function according to the characteristic of FPGA. In addition, the IDL2VHDL compiler provides the mapping from CORBA IDL to VHDL, the VHSIC hardware description language, and the additional procedures for processing the component. Finally, the improved ORBit, CORBA ORB on GPP, can be direct connecting with the HAO on FPGA.

• Journal of Internet Computing and Services
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• v.5 no.3
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• pp.45-56
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• 2004

In this paper, we propose ATM switch architecture including ALL type 2 switch which can efficiently transmit low-bit rate data, even if the network has many endpoints. We simulate the architecture of ATM switch fabric that is modeled in computer program and analyze the performance according to offered loads. ATM switch proposed in this paper can support cell switching for all types of m cells which consist of ALL type 1. ALL type 2, ALL type 3/4 and ALL type 5 cells. We propose two switch fabric methods; One supports the ALL type 2 cell processing per input port, the other global ALL type 2 cell processing for every input port. The simulation results show that the latter is superior to the former. But the former has a merit for easy implementation and extensibility. In this paper, the AAL Type 2 switch module which adapts the former method is designed using VHDL language and implemented in FPGA chip. The designed AAL Type 2 switch module operates at 52MHz. The proposed ATM switch fabric is widely applicable to mobile communication, narrow band services over ATM network and wireless ATM as well as general ATM switching fabric.

• Journal of Korea Multimedia Society
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• v.16 no.4
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• pp.483-492
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• 2013

SURF is an algorithm which extracts feature points and generates their descriptors from input images, and it is being used for many applications such as object recognition, tracking, and constructing panorama pictures. Although SURF is known to be robust to changes of scale, rotation, and view points, it is hard to implement it in real time due to its complex and repetitive computations. Using 3.3 GHz Pentium, in our experiment, it takes 240ms to extract feature points and create descriptors in a VGA image containing about 1,000 feature points, which means that software implementation cannot meet the real time requirement, especially in embedded systems. In this paper, we present a hardware architecture that can compute the SURF algorithm very fast while consuming minimum hardware resources. Two key concepts of our architecture are parallelism (for repetitive computations) and efficient line memory usage (obtained by analyzing memory access patterns). As a result of FPGA synthesis using Xilinx Virtex5LX330, it occupies 101,348 LUTs and 1,367 KB on-chip memory, giving performance of 30 frames per second at 100 MHz clock.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2380-2388
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• 2015

A hardware implementation of MOD(moving object detection) algorithm using EGML(effective Gaussian mixture learning)- based background subtraction to detect moving objects in video is described. Some approximations of EGML calculations are applied to reduce hardware complexity, and pipelining technique is adopted to improve operating speed. The MOD processor designed in Verilog-HDL has been verified by FPGA-in-the-loop verification using MATLAB/Simulink. The MOD processor has 2,218 slices on the Virtex5-XC5VSX95T FPGA device and its throughput is 102 MSamples/s at 102 MHz clock frequency. Evaluation results of the MOD processor for 12 images in the IEEE CDW-2012 dataset show that the average recall value is 0.7631, the average precision value is 0.7778 and the average F-measure value is 0.7535.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2373-2379
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• 2015

COMS(Communication, Ocean and Meteorological Satellite), the first Korean geostationary meteorological satellite, provides free meteorological information through HRIT/LRIT(High/Low Rate Information Transmission) service. This work presents the development of data receiver circuit that is essential to the implementation of a low-cost meteorological information receiver system. The data receiver circuit processes the data units according to the specification of physical layer and data link layer of HRIT/LRIT service. For this purpose, the circuit consists of a Viterbi decoder, a sync. word detector, a derandomizer, a Reed-Solomon decoder and so on. The circuit also supports PCI express interface to pass the information data on to the host PC. The circuit was implemented on an FPGA(field programmable gate array) and its function was verified through simulations and hardware implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.11A
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• pp.1167-1175
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• 2006

The ML-DFE(Maximum Likelihood-Decision Feedback Equalization) can be viewed as either a suboptimal signal detection method for reducing hardware complexity of ML or an enhanced detection method for reducing the effect of error propagation of SIC(Successive Interference Cancellation) in spatially multiplexed MIMO systems such as V-BLAST. The ML-DFE can achieve a higher diversity in rich scattering environments as well as reducing the error propagation effect by combing ML decoding with the DFE. In this paper, an MML-DFE(Modified Maximum Likelihood-Decision Feedback Equalization) is proposed to reduce the hardware complexity of the ML-DFE, without compromising performance. It is shown by FPGA implementation that the proposed MML-DFE can achieve the same performance as the ML-DFE with significantly reduced hardware complexity.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1031-1038
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• 2005

In this paper, we propose real-time 3D image converting architecture by a unit of pixel for 2D/3D compatible PC and LCD of cellular phone with parallax burier, and implement a system for overall display operation after designing a circuit based on FPGA. After digitizing anolog image signal from PC, we recompose it to 3D image signal according to input image type. Since the architecture which rearranges 2D image to 3D depends on parallax burier, we use interleaving method which mixes pixels by a unit of R, G, and B cell. The propose architecture is designed into a circuit based on FPGA with high-speed memory access technique and use 4 SDRAMs for high performance data storing and processing. The implemented system consists of A/D converting system, FPGA system to formatting 2D signal to 3D, and LCD panel with parallax barrier, for 3D display.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2018.10a
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• pp.393-394
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• 2018

In this paper, the new system which improve the previously reported "Implementation to human-computer interface system with motion tracking using OpenCV and FPGA" is introduced and in this system, a character selection system for the physically uncomfortable patients is proposed. Using OpenCV, the eye area is detected, the pupil position is determined, and then the results are sent to the FPGA, and the character is selected finally. The method to minimize the pupil movement of the patient is used to output the character according to the user's intention. Using OpenCV, various computer vision algorithms can be easily applied, and using programmable FPGA, a pupil motion recognition and character selection system are implemented with a low cost.