• Proceedings of the KIPE Conference
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• 1999.07a
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• pp.274-277
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• 1999

The paper describes a implementation of space vector pulse-width modulation (SVPWM) voltage source inverter using Field Programmable Gate Array(FPGA) for a induction motor control system. The implemented chip is included logic circuits for SVPWM, dead time compensation and speed detection using Quick Logic, QL16X24B. The maximum operating frequency and delay time can be set to 110MHz and 6 nsec. The designed FPGA for SVPWM can be incorporated with a digital signal processing to provide a simple and effective solution for high performance voltage source inverter drives. Simulation and Implementation results are shown to verify the usefulness of FPGA as a Application Specific Integrated Circuit(ASIC) in power electronics applications

• Proceedings of the IEEK Conference
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• 2002.06b
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• pp.281-284
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• 2002

Rijndael algorithm is known to a new private key block cipher which is substitute for DES. Rijndael algorithm is adequate to both hardware and software implementation, so hardware implementation of Rijndael algorithm is applied to high speed data encryption and decryption. This paper describes three implementation methods of Rijndael S-box, which is important factor in performance of Rijndael coprocessor. It shows synthesis results of each S-box implementation in Xilinx FPGA. Tllc lilree S-box implementation methods are implementation using lookup table only, implementation using both lookup table and combinational logic, and implementation using combinational logic only.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.1254-1258
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• 2004

This paper presents of position control of Permanent Magnet Synchronous Motor (PMSM) the implementation with Field Programmable Gate Array (FPGA) is proposed. Cascade control with inner loop as a current control and an outer loop as a position control is chosen for simplicity and fast response. FPGA is a single chip (single processing unit), which will perform the following tasks: receive and convert control signal, create a reference current signal, control current and create switch signal and act as position controller in a addition of zero form. The 10 kHz sampling frequency and 25 bit of floating point data are defined in this implementation.The experimental results show that the performance of FPGA based position control is comparable with the hardware based position control, with the advantage of control algorithm flexibility

• International Journal of Control, Automation, and Systems
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• v.4 no.5
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• pp.567-574
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• 2006

This paper presents the hardware implementation of a neural network controller for a nonlinear system with a micro-controller unit (MCU) and a field programmable gate array (FPGA) chip. As an on-line learning algorithm of a neural network, the reference compensation technique has been implemented on an MCU, while PID controllers with other functions such as counters and PWM generators are implemented on an FPGA chip. Interface between an MCU and a field programmable gate array (FPGA) chip has been developed to complete hardware implementation of a neural controller. The developed neural control hardware has been tested for balancing the inverted pendulum while controlling a desired trajectory of a cart as a nonlinear system.

• 제어로봇시스템학회:학술대회논문집
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• 1997.10a
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• pp.520-523
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• 1997

This paper presents FPGA implementation of fuzzy controller using Product-Sum inference method. Product-Sum inference method has much better performance than other inference methods. This fuzzy controller is composed of several digital modules, e.g. fuzzifier, rule base, adder, multiplier, select center and divider, and is operated by error and error variation. We synthesized the fuzzy controller and performed wave simulation using Xilinx VHDL tool(ViewLogic, ViewSim).

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.799-802
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• 2003

In this paper a FPGA implementation of WEP protocol is described. IEEE 802.11 specifies a wired LAN equivalent data confidentiality algorithm. WEP(Wired Equivalent Privacy) is defined as protecting authorized users of a wireless LAN from casual eavesdropping. WEP use RC4 algorithm for data encryption and decryption, also it use CRC-32 algorithm for error detection. The WEP protocol is implemented using Xilinx VirtexE XCV1000E-6HQ240C FPGA chip with PCI bus interface.

• Proceedings of the IEEK Conference
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• 2004.06b
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• pp.521-524
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• 2004

For implementation of Cryptographic algorithms, security against implementation attacks such as side-channel attacks as well as the speed and the size of the circuit is important. Power Analysis attacks are powerful techniques of side-channel attacks to exploit secret information of crypto-processors. In this thesis the FPGA implementation of versatile elliptic crypto-processor is described. Explain the analysis of power consumption of ALTERA FPGA(FLEX10KE) that is used in our hand made board. Conclusively this thesis presents clear proof that implementations of Elliptic Curve Crypto-systems are vulnerable to Differential Power Analysis attacks as well as Simple Power Analysis attacks.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.855-858
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• 1999

In this paper, we present a FPCA implementation of IDEA algorithm. Target technology is Altera FLEX 10K FPCA. The correctness of the implementation is verified by the timing simulation with max+plus II.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.56 no.1
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• pp.106-111
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• 2007

In this study, we designed a digital fuzzy logic controller based on FPGA and microprocessor for MPPT of the sofar power generation system. A fuzzy algorithm to control the power tracking function of a boost converter has been built into the FPGA, and applied to the small scaled solar power generation system. The embodied controller showed a stable operation characteristic with the small output voltage ripple for the intensity change of solar radiation. This result proves that the implementation of the power tracking controller using FPGA is an effective way compared to the existing one using microprocessor.

• Journal of the Korea Society of Computer and Information
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• v.21 no.11
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• pp.39-47
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• 2016

In this paper, we propose an approach for real time computation of rayleigh CLAHE using a FPGA. The contrast enhancement technique should be applied in thermal equipment having a low contrast image. And thermal equipment must be processed in real time. The CLAHE is an improved algorithm based Histogram Equalization, but the HW design is complex. A value greater than a given threshold in CLAHE should be equally distributed on the other histogram bin, this process requires iterations for the distribution. But implementation of this processing in the FPGA is constrained, so this section was implemented on the assumption of the histogram distribution or modified the operation process or implemented separately in the CPU. In this paper, we designed a distinct redistribution operation in two stages. So FPGA was designed for easy, this was designed to be distributed evenly without the assumptions and constraints. In addition, we have designed a CLAHE with the rayleigh distribution to the FPGA. The simulation shows that the proposed method provides a better image quality in the thermal image.