• 전기전자학회논문지
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• 제22권3호
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• pp.578-584
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• 2018

이미지 분할은 영상의 해석과 이미지 인식 분야에서 다양한 방법으로 연구되고 있으며, 특정한 목적에 따른 이미지의 특성을 분리하기 위해 사용된다. 본 논문에서는 열화상 이미지의 특징점인 고온을 검출하여 이미지를 분할하는 알고리즘을 제안한다. 또한 연산속도의 향상을 위해 제안하는 알고리즘을 Zynq-7000 Evaluation Board 환경에서 FPGA Hardware Block Design을 진행하였다. 고온 검출 알고리즘은 16ms에서 0.001ms의 속도 향상을 보였으며 전체 블록은 50ms에서 0.322ms로 속도 향상을 보이는 것을 확인하였다. 또한 영상 테스트벤치를 사용하여 소프트웨어와 하드웨어 이미지에 대해 유사한 PSNR 결과를 입증하였다.

• Nuclear Engineering and Technology
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• 제45권4호
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• pp.477-488
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• 2013

The PLC (Programmable Logic Controller) has been widely used to implement real-time controllers in nuclear RPSs (Reactor Protection Systems). Increasing complexity and maintenance cost, however, are now demanding more powerful and cost-effective implementation such as FPGA (Field-Programmable Gate Array). Abandoning all experience and knowledge accumulated over the decades and starting an all-new development approach is too risky for such safety-critical systems. This paper proposes an RPS software development process with a platform change from PLC to FPGA, while retaining all outputs from the established development. This paper transforms FBD designs of the PLC-based software development into a behaviorally-equivalent Verilog program, which is a starting point of a typical FPGA-based hardware development. We expect that the proposed software development process can bridge the gap between two software developing approaches with different platforms, such as PLC and FPGA. This paper also demonstrates its effectiveness using an example of a prototype version of a real-world RPS in Korea.

• 제어로봇시스템학회논문지
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• 제8권12호
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• pp.1036-1040
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• 2002

To process data of digital linescan camera, the frame grabber is essential to handle the data in low-level and in high speed more than 30 MHz stably. Traditional approaches to the development of hardware in vision system for the special purpose are mai y based on PC system, and are expensive and gigantic. Therefore, there are many difficulties in applying those in the field. So we investigate, in this paper, the implementation of FPGA for real-time processing of digital linescan camera. The system is not based on PC, but electronic device such as micropncessor. So it is expected that the use of FPGAs for low-level processing represents a fast, stable and inexpensive system. The experiments are carried out on the web guiding system in order to show the efficiency of the new image processor.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2016년도 전력전자학술대회 논문집
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• pp.509-510
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• 2016

본 논문은 계통연계형 인버터의 위상추종기법인 SRF-PLL을 모델링하고, FPGA에 구현하기 위해 System Generator를 이용하여 설계하였다. SRF-PLL의 비례-적분 이득은 소신호 해석을 하여 일반화를 통해 입력전압의 크기에 관계없이 적용가능하며, 주파수 응답에서 65도 위상여유를 갖는 안정한 이득을 산정하였다. FPGA 구현을 위해 MATLAB/SIMULINK와 연동 가능한 System Generator를 이용하여 SRF-PLL을 모델링하였으며, MATLAB 기반의 시뮬레이션과 실험을 통하여 위상추종 특성을 분석하였다.

• ETRI Journal
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• 제30권2호
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• pp.315-325
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• 2008

In this paper, we first investigate the side channel analysis attack resistance of various FPGA hardware implementations of the ARIA block cipher. The analysis is performed on an FPGA test board dedicated to side channel attacks. Our results show that an unprotected implementation of ARIA allows one to recover the secret key with a low number of power or electromagnetic measurements. We also present a masking countermeasure and analyze its second-order side channel resistance by using various suitable preprocessing functions. Our experimental results clearly confirm that second-order differential side channel analysis attacks also remain a practical threat for masked hardware implementations of ARIA.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.397-400
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• 2006

Recent trend on high speed packet processing for providing multiple internet services is to use network processor instead of being implemented by legacy ASIC or FPGA. Most frequently used network processor interface is the SPI4.2. This paper address the data-rate conversion interface device between SPI4.2 and SPI3/CSIX, implemented using XILINX XC2VP40 FPGA. Furthermore, we address the methodology and necessity of flow control occurred due to the data rate difference between 10Gbps and 3.2 Gbps.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.152.1-152
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• 2001

This paper presents a high performance and cost effective way by using an FPGA circuit to implement torque controller so that the SRM can operate at high speed. In order to increase the operating speed, we need to implement both the torque and the current controllers by using an FPGA. However, it is difficult to implement all of the torque controller in the FPGA. Moreover, implementation of a time critical part is sufficient for improving the performance. One of the time critical part is the switching angle control. In this study, torque controller which calculate the switching on and commutation angles is implemented in PC because these angle are a function of rotor velocity which is varied slowly, and switching angle controller ...

• The Journal of the Acoustical Society of Korea
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• 제23권3E호
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• pp.79-84
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• 2004

In this paper, the AEC(acoustic echo canceller) is designed and implemented using VHDL(VHSIC hardware description language). The designed Echo Canceller employs the pipeline and the master-slave structure, and is realized with FPGA. As an adaptive algorithm, the Normalized LMS algorithm is used. For the coefficient adjustment, the Stochastic Iteration Algorithm(SIA) which uses only current residual values is used and the number of registers are evidently reduced and convergence speed is also much improved comparing to existing methods by using EAB of FPGA for FIR filter structure of transceiver. The designed Echo Canceller is verified with the test board implemented for this paper. From the timing simulation echo signals at about 1500 sampling data are converged and ERLE is improved by about 42-dB.

• 대한임베디드공학회논문지
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• 제12권4호
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• pp.239-246
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• 2017

Time synchronization between distributed embedded systems in the Real Time Locating System (RTLS) based on Time Difference of Arrival (TDOA) is one of the most important factors to consider in system design. Clock jitter error between each system causes many difficulties in maintaining such a time synchronization. In this paper, we implemented a system to synchronize clocks between FPGA based distributed embedded systems using the recovery clock of CDR (clock data recovery) used in high speed serial communication to solve the clock jitter error problem. It is experimentally confirmed that the cumulative time error that occurs when the synchronization is not performed through the synchronization logic using the CDR recovery clock can be completely eliminated.

• 제어로봇시스템학회논문지
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• 제13권7호
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• pp.649-655
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• 2007

In this paper, a time-delayed controller for position control of humanoid robot arms is designed and implemented on a field programmable gate array(FPGA) chip. The time-delayed control algorithm is simple to implement, and robust to reject disturbances. The time-delayed control method uses the one sample time-delayed previous information to cancel out uncertainties in the system. Since the sampling time is so fast with the current hardware technology, the time-delayed controller can be implemented. However, inertia values should be correctly estimated to have the better performance. The position tracking tasks of humanoid robot arms are tested to compare performances of several control algorithms including the time-delayed controller.