Implementation of Acoustic Echo Canceller with FPGA

In this paper, the AEC(acoustic echo canceller) is designed and implemented using VHDL(VHSIC hardware description language). The designed Echo Canceller employs the pipeline and the master-slave structure, and is realized with FPGA. As an adaptive algorithm, the Normalized LMS algorithm is used. For the coefficient adjustment, the Stochastic Iteration Algorithm(SIA) which uses only current residual values is used and the number of registers are evidently reduced and convergence speed is also much improved comparing to existing methods by using EAB of FPGA for FIR filter structure of transceiver. The designed Echo Canceller is verified with the test board implemented for this paper. From the timing simulation echo signals at about 1500 sampling data are converged and ERLE is improved by about 42-dB.