• Journal of Power Electronics
• /
• 제10권3호
• /
• pp.228-234
• /
• 2010

This paper investigates the conducted-noise characteristics of a digitally-controlled randomly-switched dc-dc converter. In order to investigate the effect of the suggested digital controller on the conducted-noise characteristics of a dc-dc converter, three factors have been studied: the field-programmable gate array (FPGA) clock speed, the randomization ratio percentage, and the effect of using a closed loop feedback controller. A field-programmable gate array is much more flexible than analog control circuits, has a lower cost, and can be used for power supply applications. A novel FPGA-based implementation has been suggested for obtaining the experimental validations and realizing the studied concepts. Furthermore, the experimental results have been discussed and design guidelines have been included.

• Journal of Power Electronics
• /
• 제10권1호
• /
• pp.65-71
• /
• 2010

This paper presents the design and implementation of voltage source inverter type SVPWM based speed control of an induction motor using a fuzzy PI controller. This scheme enables us to adjust the speed of the motor by controlling the frequency and amplitude of the stator voltage; the ratio of the stator voltage to the frequency should be kept constant. A model of the fuzzy control system is implemented in real time with a Xilinx FPGA XC3S 400E. It is introduced to maintain a constant speed to when the load varies.

• 한국통신학회논문지
• /
• 제32권4C호
• /
• pp.379-388
• /
• 2007

In this paper, we propose an adaptive turbo decoding algorithm for high order modulation scheme combined with originally design for a standard rate-1/2 turbo decoder for B/QPSK modulation. A transformation applied to the incoming I-channel and Q-channel symbols allows the use of an off-the-shelf B/QPSK turbo decoder without any modifications. Adaptive turbo decoder process the received symbols recursively to improve the performance. As the number of iterations increase, the execution time and power consumption also increase as well. The source of the latency and power consumption reduction is from the combination of the radix-4, dual-path processing, parallel decoding, and early-stop algorithms. We implemented the proposed scheme on a field-programmable gate array (FPGA) and compared its decoding speed with that of a conventional decoder. From the result of implementation, we confirm that the decoding speed of proposed adaptive decoding is faster than conventional scheme by 6.4 times.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2002년도 ITC-CSCC -2
• /
• pp.940-943
• /
• 2002

This paper presents hardware implementations of the two representative cryptographic algorithms, Advanced Encryption Standard (Rijndael), and the present American federal standard (Triple DES) using a PCI- based FPGA board named "EBSW-1" This board bases on a FPGA chip (Xilinx Virtex300 XCV300PQ240-4). The implementation results of these two algorithms were tested successfully. AES circuit could proceed an encryption as well as a decryption two times faster than the Triple-DES circuit, while the former circuit used higher rates of CLBs. Besides, if these architectures use pipeline-registers, the processing speed will be increased about 1.5 times than the presented circuits.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
• /
• pp.525-528
• /
• 2002

This study describes an implementation of object tracking algorithm on FPGA. The global system detect the zone there is more motion in, attending to the generated optical flow, and centers its attention to it to improve the details In this case, To obtain image in Camera, Image aquisition board make use of SAA7113 Video Input processor and algorithm is applied to motion estimation and difference picture. Also, This work can be applied kalman filter to reliability of tracking.

• Journal of Electrical Engineering and Technology
• /
• 제13권1호
• /
• pp.362-371
• /
• 2018

This work proposes FPGA implementation of Carrier Disposition PWM for closed loop seven level diode clamped multilevel inverter in speed control of induction motor. VLSI architecture for carrier Disposition have been introduced through which PWM signals are fed to the neutral point seven level diode clamped multilevel using which the speed of the induction motor is controlled. This proposed VLSI architecture makes the power circuit to work better with reduced stresses across the switches and a very low voltage and current total harmonic distortion (THD). The output voltages, currents, torque & speed characteristics for seven level neutral point diode clamped multilevel inverter for AC drive was studied. It has observed the proposed scheme introduces less distortion and harmonics. The results were validated using real time results.

• Journal of Positioning, Navigation, and Timing
• /
• 제13권2호
• /
• pp.149-158
• /
• 2024

Global Navigation Satellite System (GNSS) receivers are becoming increasingly sophisticated, equipped with advanced features and precise specifications, thus demanding efficient and high-performance hardware platforms. This paper presents the design and implementation of a Field-Programmable Gate Array (FPGA)-based GNSS receiver development platform for multi-band signal processing. This platform utilizes a FPGA to provide a flexible and re-configurable hardware environment, enabling real-time signal processing, position determination, and handling of large-scale data. Integrated signal processing of L/S bands enhances the performance and functionality of GNSS receivers. Key components such as the RF frontend, signal processing modules, and power management are designed to ensure optimal signal reception and processing, supporting multiple GNSS. The developed hardware platform enables real-time signal processing and position determination, supporting multiple GNSS systems, thereby contributing to the advancement of GNSS development and research.

• 한국정보통신학회논문지
• /
• 제22권1호
• /
• pp.1-8
• /
• 2018

최근 합성곱 신경망은 컴퓨터 비전에 관련된 여러 분야에서 높은 성능을 보여 주고 있으나 합성곱 신경망이 요구하는 많은 연산양은 임베디드 환경에 도입되는 것을 어렵게 하고 있다. 이를 해결하기 위해 ASIC이나 FPGA를 통한 합성곱 신경망의 구현에 많은 관심이 모이고 있고, 이러한 구현을 위해서는 효율적인 고정 소수점 표현이 필요하다. 고정 소수점 표현은 ASIC이나 FPGA에서의 구현에 적합하나 합성곱 신경망의 성능이 저하될 수 있는 문제가 있다. 이 논문에서는 합성곱 계층과 배치(batch) 정규화 계층에 대해 고정 소수점 표현을 분리해서, ResNet-50 합성곱 신경망의 합성곱 계층을 표현하기 위해 필요한 비트 수를 16비트에서 10비트로 줄일 수 있게 하였다. 연산이 집중되는 합성곱 계층이 더 간단하게 표현되므로 합성곱 신경망 구현이 전체적으로 더 효율적으로 될 것이다.

• 한국통신학회:학술대회논문집
• /
• 한국통신학회 2004년도 하계종합학술발표회논문초록집
• /
• pp.338-338
• /
• 2004

• 한국산학기술학회논문지
• /
• 제7권3호
• /
• pp.512-517
• /
• 2006

본 논문에서는 태양광 발전시스템의 최대전력추종을 위해 퍼지 이론을 도입한 퍼지제어기를 설계하였다. 퍼지제어기의 디지털 설계를 위해 태양광 발전시스템의 각 부분을 구성하고, FPGA를 사용하여 제어기를 구현하였다. 구현된 제어기는 일사량의 변화에도 안정적으로 동작하며, 출력전압의 리플이 작은 결과를 보였다. 또한 FPGA의 퍼지제어기로서의 구현가능성을 발견하고 그 타당성을 입증하였다.