• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2010.07a
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• pp.411-414
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• 2010

본 논문은 비디오 처리를 위한 고성능의 메모리 제어기를 설계하였다. 메모리 제어기는 arbiter에 의해 제어되며 이것은 메모리 억세스를 요구하는 모듈들의 요구 신호를 받아 데이터를 전송하는 역할을 해주게 된다. 구현된 메모리 제어기는 버스를 사용하기 위한 승인을 받기 위해서 마스터와 신호를 주고 받는 MAU블록, grant 신호를 디코딩하고 컨트롤 신호의 상태를 정의한 arbiter 블록, SDRAM의 ac parameter를 저장하고 bank의 준비 여부, read/write 가능 여부, precharge와 refresh의 가능 여부를 확인하여 system과 read/write가 준비되었다는 신호를 출력, SDRAM의 실질적인 입력신호를 생성하는 memory accelerator 블록, 생성된 입력신호를 저장하고 마스터에서 직접 write data를 입력 받는 memory I/F 블록으로 구성된다. 이 메모리 제어기는 174.28MHz의 주파수로 동작하였다. 본 설계는 VHDL을 이용하여 설계되었고, ALTERA의 Quartus II를 이용하여 합성하였다. 또한 ModelSim을 이용하여 설계된 회로를 검증하였다. 구현된 하드웨어는 StatixIII EP3SE80F1152C2 칩을 사용하였다.

• Review of KIISC
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• v.16 no.3
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• pp.25-33
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• 2006

본 논문에서는 임베디드 시스템 온칩 적용을 위한 통합 보안 프로세서를 SIP(Semiconductor Intellectual Property)로 설계하였다. 각각의 SIP는 VHDL RTL로 모델링하였으며, 논리합성, 시뮬레이션, FPGA 검증을 통해 재사용이 가능하도록 구현하였다. 또한 ARM9과 SIP들이 서로 통신이 가능하도록 AMBA AHB의 스펙에 따라 버스동작모델을 설계, 검증하였다. 플랫폼기반의 통합 보안 SIP는 ECC, AES, MD-5가 내부 코어를 이루고 있으며 각각의 SIP들은 ARM9과 100만 게이트 FPGA가 내장된 디바이스를 사용하여 검증하였으며 최종적으로 매그나칩 $0.25{\mu}m(4.7mm\times4.7mm)$ CMOS 공정을 사용하여 MPW(Multi-Project Wafer) 칩으로 제작하였다.

• Journal of IKEEE
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• v.21 no.2
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• pp.162-165
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• 2017

CAN (controller area network) is a standard real-time serial communication protocol, and it was developed to control various in-vehicle electronic modules. In this paper, a CAN controller was designed in Verilog HDL, based on CAN ver. 2.0A and 2.0B. The designed CAN controller was implemented in FPGA, and it was verified its operation by connecting commercial chips. Its size is about 7,800 gates when synthesized in 0.18um technology.

• Proceedings of the Korea Information Processing Society Conference
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• 2005.05a
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• pp.481-484
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• 2005

본 논문에서는 부동소수점 연산을 사용하면서도 빠른 처리속도를 가지는 신경망의 파이프라인 설계를 제안한다. 부동소수점 연산은 고정소수점 연산보다 느린 처리속도와 많은 면적으로 일반적인 하드웨어 구현에서 잘 사용되지 않지만, 제안된 구조에서는 고정소수점 연산보다 더 정확한 값을 계산할 수 있는 부동소수점 연산을 사용하며 부동소수점의 느린 처리 속도를 보완할 수 있도록 파이프라인 구조를 사용한다. 파이프라인 구조의 성능을 검증하기 위해 2 가지의 서로 다른 구조의 신경망을 사용한다. 실험 환경으로는 Xilinx XC2V8000 칩과 Xilinx ISE 6.2 의 합성 도구를 사용한다. 실험 결과는 파이프라인 구조일 때의 신경망은 각각 7 클럭, 8 클럭이 소요되고, 파이프라인 구조가 아닐 때 각각의 신경망은 77 클럭, 84 클럭으로써 파이프라인 구조일 때 약 10 배의 빠른 처리를 가진다.

• Journal of IKEEE
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• v.20 no.3
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• pp.333-336
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• 2016

LIN (local interconnect network) is a standard low-speed serial communication protocol, and it was developed as an efficient sub-bus for automotive electronic modules. In this paper, a LIN controller was implemented in Verilog HDL, based on LIN ver. 2.2A. The implemented LIN controller was verified in FPGA, and it can be supplied as an IP to be integrated into SoC system. Its size is about 2,300 gates when synthesized in 0.18um technology.

• Journal of IKEEE
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• v.21 no.3
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• pp.256-259
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• 2017

SENT (single edge nibble transmission) is a serial communication protocol between automotive sensors and ECU (electronic control unit). SENT exploits digital waveform, so it has a simple and cheap architecture without transceiver circuits. Usually it is exploited as an embedded communication interface in the sensors. In this paper, a SENT interface was designed in Verilog HDL, fully complying with SAE J2716. It was implemented in FPGA, and verified on a test board. When it was synthesized, the gate count is about 2,500 gates in 0.18um technology.

• Proceedings of the Korea Institute of Convergence Signal Processing
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• 2000.12a
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• pp.241-244
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• 2000

In this paper we designed a simple 8-bit processor using HDL. The simple 13-bit processor has 19 instructions with three different addressing modes. The processor includes registers - IR, PC, SP, Y, MA, MD, AC, IN, OUT - and 256Kbyte memory. We examined the operation of the processor through simulation and then synthesized it on FPGA.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.05a
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• pp.903-906
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• 2009

In this contribution, we designed a serial port interface (SPI) suitable for embedded systems, especially for Bluetooth baseband. Proposed architecture is compatible for the APB bus in AMBA bus architecture. The 8-bit design of the SPI module is in charge of transferring the data and the instructions between the external devices and the coprocessors. We adopted the cyclic redundancy check method for the error correction. Also, we provided the interface for multimedia cards. The designed SPI module was automatically synthesized, placed, and routed. Implementation was performed through the Altera FPGA and well operated at 25MHz clock frequency.

• Journal of the Institute of Convergence Signal Processing
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• v.12 no.4
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• pp.291-297
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• 2011

In this paper, the differential quantized method and the parallel method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed And we design the DDFS by FPGA The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is saved by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). Also we design the phase-to-sine converter using the phase accumulator of parallel type for generating the high frequency. So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction and we can design the DDFS generating the high frequency.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.4
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• pp.1-6
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• 2020

This paper proposes the design of an advanced S-Box for calculating multiplicative inverse in AES encryption process. In this approach, advanced S-box module is first designed based on composite field, and then the performance evaluation is performed for S-box with multi-stage pipelining architecture. In the proposed S-Box architecture, each module for multiplicative inverse is constructed using combinational logic for realizing both small-area and high-speed. Through logic synthesis result, the designed 3-stage pipelined S-Box shows speed improvement of about 28% compared to the conventional method. The proposed advanced AES S-Box is performed modelling at the mixed level using Verilog-HDL, and logic synthesis is also performed on Spartan 3s1500l FPGA using Xilinx ISE 14.7 tool.