• Journal of Advanced Navigation Technology
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• v.22 no.6
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• pp.675-680
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• 2018

In this paper, we propose a hand gesture recognizer using restricted coulomb energy (RCE) neural network, and present hardware implementation results for real-time learning and recognition. Since RCE-NN has a flexible network architecture and real-time learning process with low complexity, it is suitable for hand recognition applications. The 3D number dataset was created using an FPGA-based test platform and the designed hand gesture recognizer showed 98.8% recognition accuracy for the 3D number dataset. The proposed hand gesture recognizer is implemented in Intel-Altera cyclone IV FPGA and confirmed that it can be implemented with 26,702 logic elements and 258Kbit memory. In addition, real-time learning and recognition verification were performed at an operating frequency of 70MHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.6
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• pp.91-100
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• 2016

In FPGA-based real-time image warping systems, image caches are utilized for fast readout of image pixel data and reduction of memory access rate. However, a cache algorithm for a general computer system is not suitable for real-time performance because of time delays from cache misses and on-line computation complexity. In this paper, a simple image cache algorithm is presented for a FPGA-based real-time image warping system. Considering that pixel data access sequence is determined from the 2D coordinate transformation and repeated identically at every image frame, a cache load sequence is off-line programmed to guarantee no cache miss condition, and reduced on-line computation results in a simple cache controller. An overall system structure using a FPGA is presented, and experimental results are provided to show accuracy and validity of the proposed cache algorithm.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.16 no.8
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• pp.1759-1764
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• 2012

This paper describes FPGA design and realization using the shading correction algorithm for a CCD scan image enhancement. The shading algorithm is used by LUT (Look-up Table). The image enhancement results from that the histogram minimum value and maximum with respect to all pixels of the CCD image should be extracted, and the shading LUT is constructed to keep constant histogram with offset data. The output of sensor be converted to corrected LUT image in preprocessing, and the converting system is realized by FPGA to be enabled to operate in real time. The result of the experimentation for the proposed system is showed to take the scanning time 2.4ms below. The system is presented to be based on a low speed processor system to scan enhanced images in real time and be guaranteed to be low cost.

• Proceedings of the Korean Information Science Society Conference
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• 2004.10a
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• pp.25-27
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• 2004

독립적인 여러 개의 음원의 convoultive mixture로부터 blind source separation(BSS)을 수행하는 것은 수년간 활발히 연구되어 오고있다. 그러나 많은 BSS 알고리즘이 존재함에도 불구하고, 직접적으로 하드웨어를 구현할 수 있는 알고리즘은 실제로 매우 드물다. 이 논문의 목표는 FPGA를 이용하여 실시간으로 효과적인 구현이 가능한 BSS 구조를 소개하는 것이다.

• Journal of IKEEE
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• v.15 no.1
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• pp.86-95
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• 2011

In this paper, we propose a testbed system for the crisis management system of the power grid(CMS-PG) using satellite communication network. For the verification of CMS-PG, the proposed system composed of the simulator of satellite communication network and the simulator of phase measurement unit. Proposed satellite communication simulator can evaluate the delay and the robustness of the communication according to the rainfall and the humidity of local site. And the proposed simulator can calculates the voltage stability by hardware implementation using FPGA. Using the proposed testbed system, we adapted its function of crisis management system for the conventional power grid.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.877-880
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• 2005

As DMB, 3D game, Internet and movie is serviced for the recent mobile devices, high resolution display devices beyond VGA become used. Implementation of real-time moving pictures of 30렌 by software programming is difficult because the performance of mobile processors is not so high. The full frame moving picture can be supported by using specific hardware. In this paper, an OLED controller that is consists of flash memory controller and OLED interface is proposed for real-time moving picture on mobile displays. The proposed OLED controller is implemented in FPGA and the performance is evaluated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.3C
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• pp.183-189
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• 2011

The LMS(Least Mean Square) algorithm is generally used because of tenacity, high mating spots and simplicity of realization. But the LMS algorithm has trade-off between nonuniform collect and EMSE(Excess Mean Square Error). To overcome this weakness, variable step size is used widely but it needs a lot of calculation load. In this paper we consider new algorithm, which can reduce calculations and adapt in case of environment changes, uses original signal and noise signal of IGC(Instantaneous Gain Control). For the real time processing of IGC algorithm, we remove the logarithmic function. The performance of proposed algorithm is tested to adaptive noise canceller in automobile. We show implemented LabVIEW FPGA system of IGC algorithm is more efficient than others.

• Journal of the Korea Society of Computer and Information
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• v.17 no.4
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• pp.11-18
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• 2012

Deep packet inspection which perform pattern matching to search for malicious patterns in the packet is most computationally intensive task. Hardware-based pattern matching is required for real-time packet inspection in high-speed network. In this paper, we have designed and implemented network intrusion detection hardware as a Microblaze-based SoC using Virtex-6 FPGA, which capture the network input packet, perform hardware-based pattern matching for patterns in the Snort rule, and provide the matching result to the software. We verify the operation of the implemented system using traffic generator and real network traffic. The implemented hardware can be used in network intrusion detection system operated in wire-speed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7A
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• pp.683-694
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• 2002

In this paper, a digital image compression codec using 2D DWT(Discrete Wavelet Transform) is designed using the FPGA technology for real time operation The implemented image compression codec using wavelet decomposition consists of a wavelet kernel part for wavelet filtering process, a quantizer/huffman coder for quantization and huffman encoding of wavelet coefficients, a memory controller for interface with external memories, a input interface to process image pixels from A/D converter, a output interface for reconstructing huffman codes, which has irregular bit size, into 32-bit data having regular size data, a memory-kernel buffer to arrage data for real time process, a PCI interface part, and some modules for setting timing between each modules. Since the memory mapping method which converts read process of column-direction into read process of the row-direction is used, the read process in the vertical-direction wavelet decomposition is very efficiently processed. Global operation of wavelet codec is synchronized with the field signal of A/D converter. The global hardware process pipeline operation as the unit of field and each field and each field operation is classified as decomposition levels of wavelet transform. The implemented hardware used FPGA hardware resource of 11119(45%) LAB and 28352(9％) ESB in FPGA device of APEX20KC EP20k600CB652-7 and mapped into one FPGA without additional external logic. Also it can process 33 frames(66 fields) per second, so real-time image compression is possible.

• Journal of IKEEE
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• v.25 no.4
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• pp.634-643
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• 2021

In this paper, an FPGA-based acceleration scheme of range Doppler algorithm (RDA) is proposed for the real time synthetic aperture radar (SAR) imaging. Hardware architectures of matched filter based on systolic array architecture and a high speed sinc interpolator to compensate range cell migration (RCM) are presented. In addition, the proposed hardware was implemented and accelerated on Xilinx Alveo FPGA. Experimental results for 4096×4096-size SAR imaging showed that FPGA-based implementation achieves 2 times acceleration compared to GPU-based design. It was also confirmed the proposed design can be implemented with 60,247 CLB LUTs, 103,728 CLB registers, 20 block RAM tiles and 592 DPSs at the operating frequency of 312 MHz.