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http://dx.doi.org/10.6109/jkiice.2012.16.8.1759

FPGA Design and Realization for Scanning Image Enhancement using LUT Shading Correction Algorithm  

Kim, Young-Bin (목원대학교)
Ryu, Conan K.R. (목원대학교)
Publication Information
Journal of the Korea Institute of Information and Communication Engineering / v.16, no.8, 2012 , pp. 1759-1764 More about this Journal
Abstract
This paper describes FPGA design and realization using the shading correction algorithm for a CCD scan image enhancement. The shading algorithm is used by LUT (Look-up Table). The image enhancement results from that the histogram minimum value and maximum with respect to all pixels of the CCD image should be extracted, and the shading LUT is constructed to keep constant histogram with offset data. The output of sensor be converted to corrected LUT image in preprocessing, and the converting system is realized by FPGA to be enabled to operate in real time. The result of the experimentation for the proposed system is showed to take the scanning time 2.4ms below. The system is presented to be based on a low speed processor system to scan enhanced images in real time and be guaranteed to be low cost.
Keywords
Shading Correction Algorithm; LUT; Scanning Image; FPGA; CCD;
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Times Cited By KSCI : 3  (Citation Analysis)
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