• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.66-76
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• 2009

The motion estimation in video encoding system occupies the biggest part. So, we require the motion estimator with efficient structure for real-time operation. And for motion estimator's implementation, it is desired to design hardware module of an exclusive use that perform the encoding process at high speed. This paper proposes motion estimation detection block(MED), 41 SADs(Sum of Absolute Difference) calculation block, minimum SAD calculation and motion vector generation block based on parallel processing. The parallel processing can reduce effectively the amount of the operation. The minimum SAD calculation and MED block uses the pre-computation technique for reducing switching activity of the input signal. It results in high-speed operation. The MED and 41 SADs calculation blocks are composed of adder tree which causes the problem of critical path. So, the structure of adder tree has changed the most commonly used ripple carry adder(RCA) with carry skip adder(CSA). It enables adder tree to operate at high speed. In addition, as we enabled to easily control key variables such as control signal of search range from the outside, the efficiency of hardware structure increased. Simulation and FPGA verification results show that the delay of MED block generating the critical path at the motion estimator is reduced about 19.89% than the conventional strukcture.

• Journal of Advanced Navigation Technology
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• v.26 no.4
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• pp.211-218
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• 2022

Continuous wave (CW) radar has the advantage of reliability and accuracy compared to other sensors such as camera and lidar. In addition, binarized neural network (BNN) has a characteristic that dramatically reduces memory usage and complexity compared to other deep learning networks. Therefore, this paper proposes binarized neural network based human identification and motion classification system using CW radar. After receiving a signal from CW radar, a spectrogram is generated through a short-time Fourier transform (STFT). Based on this spectrogram, we propose an algorithm that detects whether a person approaches a radar. Also, we designed an optimized BNN model that can support the accuracy of 90.0% for human identification and 98.3% for motion classification. In order to accelerate BNN operation, we designed BNN hardware accelerator on field programmable gate array (FPGA). The accelerator was implemented with 1,030 logics, 836 registers, and 334.904 Kbit block memory, and it was confirmed that the real-time operation was possible with a total calculation time of 6 ms from inference to transferring result.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.40 no.11
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• pp.2169-2177
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• 2015

This paper proposes a new pattern matching module to overcome the increased runtime of previous algorithm using RAM, which was designed to overcome cost limitation of hash-based algorithm using CAM (Content Addressable Memory). By adopting Merge FSM algorithm to reduce the number of state, the proposed module contains state block and entry block to use in RAM. In the proposed module, one input string is compared with multiple entry strings simultaneously using entry block. The effectiveness of the proposed pattern matching unit is verified by executing Snort 2.9 rule set. Experimental results show that the number of memory reads has decreased by 15.8%, throughput has increased by 47.1%, while memory usage has increased by 2.6%, when compared to previous methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.89-96
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• 2010

In this paper, we proposed a method about improving face tracking efficiency of face detection for AF system using the faces to the ROI. The conventional face detection system detecting faces based skin color uses the ratio of skin pixels of the present frame to detected face regions of the past frame to track the faces. The tracking method is superior in the stability of the regions but it is inferior in the face tracking efficiency. We proposed a face tracking method using the area of the overlapping region in the detected face regions of the past frame and the present frame to improve the tracking efficiency. The proposed face tracking efficiency demonstration was performed by making a film of face detection with face tracking in real-time and using the moving traces of the detected faces.

• Journal of IKEEE
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• v.27 no.4
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• pp.624-629
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• 2023

Estimation of signal parameters via rotational invariance techniques (ESPRIT) is an algorithm that estimates the angle of a signal arriving at an array antenna using the shift invariance property of an array antenna. ESPRIT offers the good trade-off between performance and complexity. However, the ESPRIT algorithm still requires high-complexity operations such as covariance matrix and eigenvalue decomposition, so implementation with a hardware processor is essential to estimate the angle of arrival in real time. In addition, ESPRIT processors should have high performance. The performance is related to the number of antennas, and the number of antennas required for each application are different. Therefore, we proposed an ESPRIT processor that provides 2 to 8 variable antenna configurations to meet the performance and complexity requirements according to the applied field. The proposed ESPRIT processor was designed using the Verilog-HDL and implemented on a field programmable gate array (FPGA).

• KIPS Transactions on Software and Data Engineering
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• v.11 no.1
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• pp.51-58
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• 2022

Drivable area detection, one of the main functions of advanced driver assistance systems, means detecting an area where a vehicle can safely drive. The drivable area detection is closely related to the safety of the driver and it requires high accuracy with real-time operation. To satisfy these conditions, V-disparity-based method is widely used to detect a drivable area by calculating the road disparity value in each row of an image. However, the V-disparity-based method can falsely detect a non-road area as a road when the disparity value is not accurate or the disparity value of the object is equal to the disparity value of the road. In a road environment including vegetation, such as a highway and a country road, the vegetation area may be falsely detected as the drivable area because the disparity characteristics of the vegetation are similar to those of the road. Therefore, this paper proposes a drivable area detection method and hardware architecture with a high accuracy in road environments including vegetation areas by reducing the number of false detections caused by V-disparity characteristic. When 289 images provided by KITTI road dataset are used to evaluate the road detection performance of the proposed method, it shows an accuracy of 90.12% and a recall of 97.96%. In addition, when the proposed hardware architecture is implemented on the FPGA platform, it uses 8925 slice registers and 7066 slice LUTs.

• The KIPS Transactions:PartC
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• v.13C no.1 s.104
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• pp.83-94
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• 2006

This paper describes ATM cell encipherment method using Rijndael Algorithm adopted as an AES(Advanced Encryption Standard) by NIST in 2001. ISO 9160 describes the requirement of physical layer data processing in encryption/decryption. For the description of ATM cell encipherment method, we implemented ATM data encipherment equipment which satisfies the requirements of ISO 9160, and verified the encipherment/decipherment processing at ATM STM-1 rate(155.52Mbps). The DES algorithm can process data in the block size of 64 bits and its key length is 64 bits, but the Rijndael algorithm can process data in the block size of 128 bits and the key length of 128, 192, or 256 bits selectively. So it is more flexible in high bit rate data processing and stronger in encription strength than DES. For tile real time encryption of high bit rate data stream. Rijndael algorithm was implemented in FPGA in this experiment. The boundary of serial UNI cell was detected by the CRC method, and in the case of user data cell the payload of 48 octets (384 bits) is converted in parallel and transferred to 3 Rijndael encipherment module in the block size of 128 bits individually. After completion of encryption, the header stored in buffer is attached to the enciphered payload and retransmitted in the format of cell. At the receiving end, the boundary of ceil is detected by the CRC method and the payload type is decided. n the payload type is the user data cell, the payload of the cell is transferred to the 3-Rijndael decryption module in the block sire of 128 bits for decryption of data. And in the case of maintenance cell, the payload is extracted without decryption processing.

• Proceedings of the Korean Vacuum Society Conference
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• 2014.02a
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• pp.109-110
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• 2014

주사전자현미경(Scanning Electron Microscopy: SEM)은 고체상태에서 미세조직과 형상을 관찰하는 데에 가장 다양하게 쓰이는 분석기기로서 최근에 판매되고 있는 고분해능 SEM은 수 나노미터의 분해능을 가지고 있다. 그리고 SEM의 초점심도가 크기 때문에 3차원적인 영상의 관찰이 용이해서 곡면 혹은 울퉁불퉁한 표면의 영상을 육안으로 관찰하는 것처럼 보여준다. 활용도도 매우 다양해서 금속파면, 광물과 화석, 반도체 소자와 회로망의 품질검사, 고분자 및 유기물, 생체시료 nnnnnnnnn와 유가공 제품 등 모든 산업영역에 걸쳐 있다(Fig. 1). 입사된 전자빔이 시료의 원자와 탄성, 비탄성 충돌을 할 때 2차 전자(secondary electron)외에 후방산란전자(back scattered electron), X선, 음극형광 등이 발생하게 되는 이것을 통하여 topography (시료의 표면 형상), morphology(시료의 구성입자의 형상), composition(시료의 구성원소), crystallography (시료의 원자배열상태)등의 정보를 얻을 수 있다. SEM은 2차 전자를 이용하여 시료의 표면형상을 측정하고 그 외에는 SEM을 플랫폼으로 하여 EDS (Energy Dispersive X-ray Spectroscopy), WDS (Wave Dispersive X-ray Spectroscope), EPMA (Electron Probe X-ray Micro Analyzer), FIB (Focus Ion Beam), EBIC (Electron Beam Induced Current), EBSD (Electron Backscatter Diffraction), PBMS (Particle Beam Mass Spectrometer) 등의 많은 분석장치들이 SEM에 부가적으로 장착되어 다양한 시료의 측정이 이루어진다. 이 중 결정구조, 조성분석을 쉽고 효과적으로 할 수 있게 하는 X선 분석장치인 EDS를 SEM에 일체화시킨 장비와 EDS 및 PBMS를 SEM에 장착하여 반도체 공정 중 발생하는 나노입자의 형상, 성분, 크기분포를 측정하는 PCDS(Particle Characteristic Diagnosis System)에 대해 소개하고자 한다. - EDS와 통합된 SEM 시스템 기본적으로 SEM과 EDS는 상호보완적인 기능을 통하여 매우 밀접하게 사용되고 있으나 제조사와 기술적 근간의 차이로 인해 전혀 다른 방식으로 운영되고 있다. 일반적으로 SEM과 EDS는 별개의 시스템으로 스캔회로와 이미지 프로세싱 회로가 개별적으로 구현되어 있지만 로렌츠힘에 의해 발생하는 전자빔의 왜곡을 보정을 위해 EDS 시스템은 SEM 시스템과 연동되어 운영될 수 밖에 없다. 따라서, 각각의 시스템에서는 필요하지만 전체 시스템에서 보면 중복된 기능을 가지는 전자회로들이 존재하게 되고 이로 인해 SEM과 EDS에서 보는 시료의 이미지의 차이로 인한 측정오차가 발생한다(Fig. 2). EDS와 통합된 SEM 시스템은 중복된 기능인 스캔을 담당하는 scanning generation circuit과 이미지 프로세싱을 담당하는 FPGA circuit 및 응용프로그램을 SEM의 회로와 프로그램을 사용하게 함으로 SEM과 EDS가 보는 시료의 이미지가 정확히 일치함으로 이미지 캘리브레이션이 필요없고 측정오차가 제거된 EDS 측정이 가능하다. - PCDS 공정 중 발생하는 입자는 반도체 생산 수율에 가장 큰 영향을 끼치는 원인으로 파악되고 있으며, 생산수율을 저하시키는 원인 중 70% 가량이 이와 관련된 것으로 알려져 있다. 현재 반도체 공정 중이나 반도체 공정 장비에서 발생하는 입자는 제어가 되고 있지 않은 실정이며 대부분의 반도체 공정은 저압환경에서 이루어지기에 이 때 발생하는 입자를 제어하기 위해서는 저압환경에서 측정할 수 있는 측정시스템이 필요하다. 최근 국내에서는 CVD (Chemical Vapor Deposition) 시스템 내 파이프내벽에서의 오염입자 침착은 심각한 문제점으로 인식되고 있다(Fig. 3). PCDS (Particle Characteristic Diagnosis System)는 오염입자의 형상을 측정할 수 있는 SEM, 오염입자의 성분을 측정할 수 있는 EDS, 저압환경에서 기체에 포함된 입자를 빔 형태로 집속, 가속, 포화상태에 이르게 대전시켜 오염입자의 크기분포를 측정할 수 있는 PBMS가 일체화 되어 반도체 공정 중 발생하는 나노입자 대해 실시간으로 대처와 조치가 가능하게 한다.

• KEPCO Journal on Electric Power and Energy
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• v.8 no.2
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• pp.159-179
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• 2022

Often a network becomes complex, and multiple entities would get in charge of managing part of the whole network. An example is a utility grid. While the entire grid would go under a single utility company's responsibility, the network is often split into multiple subsections. Subsequently, each subsection would be given as the responsibility area to the corresponding sub-organization in the utility company. The issue of how to make subsystems of adequate size and minimum number of interconnections between subsystems becomes more critical, especially in real-time simulations. Because the computation capability limit of a single computation unit, regardless of whether it is a high-speed conventional CPU core or an FPGA computational engine, it comes with a maximum limit that can be completed within a given amount of execution time. The issue becomes worsened in real time simulation, in which the computation needs to be in precise synchronization with the real-world clock. When the subject of the computation allows for a longer execution time, i.e., a larger time step size, a larger portion of the network can be put on a computation unit. This translates into a larger margin of the difference between the worst and the best. In other words, even though the worst (or the largest) computational burden is orders of magnitude larger than the best (or the smallest) computational burden, all the necessary computation can still be completed within the given amount of time. However, the requirement of real-time makes the margin much smaller. In other words, the difference between the worst and the best should be as small as possible in order to ensure the even distribution of the computational load. Besides, data exchange/communication is essential in parallel computation, affecting the overall performance. However, the exchange of data takes time. Therefore, the corresponding consideration needs to be with the computational load distribution among multiple calculation units. If it turns out in a satisfactory way, such distribution will raise the possibility of completing the necessary computation in a given amount of time, which might come down in the level of microsecond order. This paper presents an effective way to split a given electrical network, according to multiple criteria, for the purpose of distributing the entire computational load into a set of even (or close to even) sized computational loads. Based on the proposed system splitting method, heavy computation burdens of large-scale electrical networks can be distributed to multiple calculation units, such as an RTDS real time simulator, achieving either more efficient usage of the calculation units, a reduction of the necessary size of the simulation time step, or both.

• Korea journal of population studies
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• v.30 no.2
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• pp.71-95
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• 2007

This paper attempts to identify the principle of family succession and family patterns of yangban in the late Chosun period through an analysis of male adaptation cases found in family registration records. The primary source of analysis is the family registration documents of Uiseong Kim's from the late 17th century to the early 20th century. As a result, it is found that there is a substantial change in the patterns of family from the early and mid Chosun period to the late Chosun period. The change is the strengthening of the principle of patriarchy succession through male adoption. Looking at the data as a whole, the average number of household members is increased and the membership of kinship also expanded. In contrast to the family patterns of the early Chosun period, not only the patterns of Uiseong Kim's family are predominately immediate family or collateral family but also the majority is extended family in the 18th and 19th centuries. The male adoption cases recorded in Uiseong Kim's family registration documents take up 33.8% of the male adoption cases in the entire family registration documents. This goes to show that the strengthening of the principle of primogeniture succession at a time when child mortality rate is very high resulted in the increase of male adoption. In conclusion, the late Chosun society was a society where the seat of primogeniture was much more important than immediate hereditary members in the family succession.